Buck-boost DC/DC Converter Ramp Shift Overlap Control
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Solution Overview
Problem
Conventional buck-boost DC/DC converters experience efficiency dips when operating near the transition point between buck and boost modes due to discontinuity in transfer function and excessive switching losses from wide overlap of ramp signals, leading to unpredictable noise and energy dissipation.
Innovation Solution
A buck-boost DC/DC converter with an overlap control mechanism that adjusts ramp signals to minimize gaps and overlaps, automatically canceling offsets and temperature drifts, and switching noise by inverting the slope of boost ramp signals and shifting their levels to optimize switch activity within clock periods, thereby avoiding buck-boost operation near the transition point.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a wide overlap between ramp signals is provided to avoid discontinuity, then the converter operates smoothly in buck-boost mode, but efficiency deteriorates due to excessive switching losses
Solution Approach 1:
The patent dynamically adjusts the overlap between ramp signals based on operating conditions. The control circuit monitors the duty cycle and automatically modifies the timing relationship between buck and boost ramp signals, transitioning from a fixed wide overlap to a variable overlap that minimizes switching losses while maintaining smooth operation.
Solution Approach 2:
The patent changes the timing parameters of ramp signals adaptively. By modifying the start and end times of ramp signal generation based on the operating mode and duty cycle, the system optimizes the overlap duration to prevent discontinuity while reducing unnecessary switching events that cause energy loss.
2Ease of manufacture
If conventional fixed ramp signals are used, then the circuit implementation is simple, but efficiency dips occur when supply voltage is close to output voltage
Solution Approach 1:
The patent implements a feedback mechanism where the control circuit continuously monitors the operating state and duty cycle, then adjusts the ramp signal timing accordingly. This closed-loop control eliminates efficiency dips by adaptively optimizing the ramp signal overlap based on real-time voltage conditions while maintaining reasonable circuit complexity.
Solution Approach 2:
The control circuit performs preliminary adjustment of ramp signal timing based on predicted operating conditions. By pre-modifying the ramp signal parameters before the efficiency dip occurs, the system proactively prevents the problem rather than reacting to it, maintaining high efficiency across the full voltage range.
3Reliability
If gap between ramp signals is reduced, then discontinuity problem is avoided, but unpredictable low frequency noise occurs
Solution Approach 1:
The patent dynamically controls the gap between ramp signals rather than using a fixed value. The control circuit adjusts the timing offset between buck and boost ramps based on the operating point, ensuring continuous PWM generation while maintaining sufficient separation to prevent low frequency noise artifacts.
Data Source
AI summary
A buck-boost DC/DC converter includes an inductor and a power stage having a set of switches selectively connecting the inductor between a voltage input, a voltage output and a reference level in accordance with buck or boost mode. The converter has a switch control providing control signals to the set of switches in the power stage. A comparator provides to the switch control a first pulse width modulation signal in buck mode and a second pulse width modulation signal in boost mode. A ramp generator provides to the comparator a first ramp signal for buck mode and a second ramp signal for boost mode. An overlap control provides a ramp shift signal to the ramp generator in response to a detection signal that indicates activity of the switches in the power stage. The ramp shift signal adjusts the first and second ramp signals relative to each other so as to minimize any gap and any overlap between the first and second ramp signals. Whenever actuation of all switches in the power stage within the same clock period is detected, the ramp signals are adjusted in a way to reduce the overlap between the ramp signals. Conversely, when no switch activity is detected in a clock period, the ramp signals are adjusted in a waye to increase the overlap between the ramp signals. As a result, when the input voltage is close to the output voltage, the converter alternatively operates in buck mode or in boost mode, avoiding a buck-boost mode.