Buck-Boost Converter State Machine for Stable Mode Switching
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Solution Overview
Problem
Existing DC/DC buck-boost converters face inefficiencies and reliability issues due to the need for high time resolution in controlling switch duty cycles near 100% or 0%, leading to impractical switch control and stability problems, especially when transitioning between buck, boost, and buck-boost modes.
Innovation Solution
A buck-boost converter controlled by an asynchronous finite state machine, which decides operation modes on a cycle-by-cycle basis using error signals derived from input and output voltages, currents, and temperatures, eliminating the need for averaging and hysteresis, and ensuring minimum switch state durations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If duty cycle is increased close to 100% in buck mode or decreased close to 0% in boost mode to achieve precise voltage regulation, then output voltage control precision is improved, but switch control becomes impractical and reliability deteriorates
Solution Approach 1:
The patent implements dynamic mode switching between buck and boost operations based on real-time comparison of input and output voltages. When Vout approaches Vin, the system automatically transitions from duty cycle modulation to mode switching, avoiding the impractical extreme duty cycles while maintaining precise voltage control through adaptive operation mode changes
2Ease of operation
If pulse skipping is used to limit switching frequency and minimum ON/OFF time, then switch control practicality is improved, but control loop stability deteriorates and ripple increases
Solution Approach 1:
The system dynamically adjusts its control strategy based on operating conditions. Instead of using pulse skipping that compromises stability, the patent employs continuous duty cycle modulation with automatic mode switching, maintaining both practical switch control durations and control loop stability across the full operating range
Solution Approach 2:
The patent changes the control parameter from duty cycle alone to a combination of duty cycle and operation mode. By introducing mode switching as an additional control degree of freedom, the system achieves practical switch timing while maintaining stability, effectively transforming the control approach to resolve the contradiction
3Adaptability or versatility
If full-bridge configuration with four switches is used to enable buck, boost, and buck-boost modes, then adaptability is improved, but device complexity increases
Solution Approach 1:
The patent implements a universal converter topology that can operate in buck, boost, and buck-boost modes using the same four-switch full-bridge configuration. The controller universally applies the same control algorithm across all modes, selecting appropriate switch states based on the desired operation mode, thereby achieving multi-functionality without proportionally increasing complexity
4Stability of the object's composition
If averaging and hysteresis are applied to make transition noise insensitive, then transition stability is improved, but response time increases and manufacturing precision requirements worsen
Solution Approach 1:
The patent applies preliminary action by setting predetermined voltage thresholds for mode transitions. Instead of averaging over time, the system proactively detects transition conditions by comparing voltages against fixed thresholds and immediately executes mode switching, achieving both noise insensitivity and fast response without compromising precision
Data Source
Figure 1A~1B
Figure 2A~2C
Figure 2D~2E
AI summary
The present invention generally relates to a buck-boost converter (2000) based ona finite state machine. In particular, the buck-boost converter (2000) comprises converting means (1100), for converting an input voltage (VIN) into an output voltage (VOUT), the converting means comprising a plurality of switches (1111-1114) and an inductor (1120) and a controller (2200) for controlling the plurality of switches (1111-1114). The operation of the controller is driven by a finite state machine (2400) configured to receive as input state change signals (VPWM_BCK, VPWM_BST) and to provide as output state signals (S1A-S3) for driving the controller (1200). The state change signals (VPWM_BCK, VPWM_BST) are generated by comparing means (2300) based on a comparison of a replica signal (VMOD) and an error signal (VEA), wherein the error signal (VEA) is computed on the basis of a signal representative of a difference between a characteristic of the converting means (1100) and a predetermined reference signal (VREF), and wherein the replica signal (VMOD) is representative of the current flowing through the inductor (1120).