Uniform Current Distribution in Synchronous Buck Converter
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Solution Overview
Problem
The existing power supply modules using metal clips for interconnecting vertically stacked power FET chips are poorly suited for customization, leading to issues with scalability, high cost, and current crowding, which results in overheating and limited ability to handle high switching currents between 10 and 25 A.
Innovation Solution
Depositing an extra metal layer on the top terminal areas of the FET chips, preferably copper or aluminum-based with a solderable finish, to equalize lateral and vertical resistance, allowing for uniform current distribution and eliminating the need for metal clips, thereby enabling the handling of currents between 15 and 30 A.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Power
If metal clips are used to interconnect vertically stacked power FET chips, then current handling capability is improved, but device complexity and cost increase
Solution Approach 1:
The patent removes the metal clips from the assembly, extracting the problematic interconnection element that caused current crowding and complexity issues. The clips are completely eliminated and replaced by a redesigned chip terminal structure with extended lateral surfaces that provide direct electrical contact between stacked chips.
Solution Approach 2:
The patent merges the interconnection function previously performed by separate metal clips into the chip terminals themselves. The extended lateral surfaces of the chip terminals directly contact adjacent chips, combining the electrical connection and mechanical support functions into a unified structure.
2Reliability
If metal clips are used to interconnect power FET chips, then electrical connection is improved, but manufacturing cost and lead time increase
Solution Approach 1:
The patent eliminates the metal clips from the manufacturing process, removing the need for separate clip attachment steps and reducing manufacturing complexity. This extraction of the clip component simplifies the assembly process and reduces lead times.
Solution Approach 2:
The chip terminals are pre-formed with extended lateral surfaces during chip fabrication, preparing the connection interface in advance. This preliminary structuring of the terminals eliminates the need for subsequent clip installation and reduces manufacturing steps.
3Power
If metal clips are used for interconnection, then current distribution is improved, but module height increases
Solution Approach 1:
The patent transitions from vertical stacking with lateral clip connections to a configuration where current distribution is achieved through extended lateral surfaces of terminals. This dimensional change in the terminal structure eliminates the need for additional vertical space that clips would require.
4Reliability
If metal clips are used to connect power FET chips, then electrical connection is improved, but customization flexibility and scalability decrease
Solution Approach 1:
The extended lateral terminal surfaces serve multiple functions: electrical connection, mechanical support, and thermal management. This universal design allows the same structure to be used across different power ratings and configurations, enabling scalability and customization without requiring different clip designs.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This solution reduces parasitic inductance, prevents current crowding, and enhances the efficiency of the power supply module, allowing it to operate at higher frequencies and handle higher currents without overheating, while also reducing the module thickness and cost.
Implementation Method 1
Depositing an extra metal layer on the top terminal areas of the FET chips, preferably copper or aluminum-based with a solderable finish, to equalize lateral and vertical resistance
Data Source
AI summary
A synchronous Buck converter in a molded package (thickness 101 between 0.8 and 1.0 mm) has vertically assembled control (110) and sync (120) power FET chips and a driver chip (630). The sync chip has one power terminal attached to the leadframe pad (104) and the opposite power terminal covered by a first copper layer (125) connected (210) to a first leadframe terminal (105), the first layer providing a smaller resistance to a current between first terminal and pad than the resistance through the sync chip. The control chip has one power terminal attached to the first layer and the opposite power terminal covered by a second copper layer (115) connected (410) to a second leadframe terminal (106), the second layer providing a smaller resistance to a current from the first to the second terminal than the resistance through the control chip. Connections (210, 410) of layers (125, 115) to leadframe terminals (105, 106) are copper wires of 20 to 50 μm diameter, enabling currents between 3 and 30 A.