ESR Zero Estimation in Digitally Controlled Buck Converters
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Solution Overview
Problem
In DC-DC buck converters, the output capacitor's Equivalent Series Resistance (ESR) introduces a zero in the converter's transfer function, which affects loop response and stability, but existing methods fail to accurately account for ESR variations during board design due to unknown or varying capacitor values, leading to instability and the need for iterative compensation network reconfiguration.
Innovation Solution
A method for estimating and compensating the ESR zero by measuring output voltage ripple, allowing a PID compensator to update control operations and ensure stability, using a digitally controlled buck converter with an ESR zero identification block to calculate the ESR zero frequency and update the control accordingly.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If traditional PID compensator design is used without ESR consideration, then the design process is simpler, but the system suffers from low phase margin, slow response speed, or instability
Solution Approach 1:
The patent implements feedback by continuously monitoring the output voltage ripple to estimate ESR zero frequency, then using this information to dynamically adjust the PID compensator parameters. This closed-loop approach ensures the system maintains stability despite component variations without requiring manual reconfiguration.
Solution Approach 2:
The system performs self-identification of ESR zero frequency and self-adjustment of compensator parameters through online measurement and automatic parameter updating. This eliminates the need for manual iterative reconfiguration by application engineers while ensuring optimal performance.
2Measurement precision
If complete frequency domain identification including ESR zero is used, then ESR variations are accurately accounted for, but the method requires open-loop operation and heavy computations making it unsuitable for online operation
Solution Approach 1:
The patent extracts only the essential information needed for ESR zero identification by measuring output voltage ripple during normal closed-loop operation, rather than performing complete frequency domain identification. This selective approach maintains accuracy while enabling online operation without heavy computational burden or open-loop requirements.
Solution Approach 2:
The system dynamically estimates ESR zero frequency in real-time during closed-loop operation by analyzing output voltage ripple characteristics. This dynamic approach allows continuous adaptation to component variations without requiring the system to enter open-loop mode or perform computationally intensive measurements.
3Ease of manufacture
If ESR variations due to temperature and tolerances are not considered, then the compensator design is easier, but the system becomes unstable under varying operating conditions
Solution Approach 1:
The patent automatically adjusts PID compensator parameters based on real-time estimation of ESR zero frequency, which varies with temperature and component tolerances. This parameter adaptation ensures the system maintains stability and performance across different operating conditions without requiring manual redesign.
Data Source
AI summary
One embodiment of the present invention is a digitally controlled DC-DC converter comprising of a power stage including at least one switch and an output capacitor. A digital controller can control the switching of the at least one switch. The digital controller can include logic to produce an indication related to a zero resulting from the equivalent series resistance (ESR) of the output capacitor and to update the control of the switching of the switch in the power stage based on the estimate.