Buck Converter Ripple Suppression Under Light Load
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Solution Overview
Problem
Conventional buck converters experience increased ripple voltage under light load conditions due to the reduction of oscillating frequency, which affects efficiency and output voltage stability.
Innovation Solution
A buck converter design that includes a current detection circuit and a switching control circuit to reduce the on-time of the MOS transistor, utilizing a comparator and counter to detect reverse currents and adjust the on-time based on detected current levels, thereby reducing ripple voltage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of energy
If the oscillating frequency of the buck converter is reduced to improve efficiency under light load conditions, then power conversion efficiency is improved, but output ripple voltage increases
Solution Approach 1:
The patent applies dynamics by making the switching frequency variable rather than fixed. The control circuit dynamically adjusts the switching frequency based on load conditions: operating at lower frequencies during light load to improve efficiency, and automatically increasing frequency when ripple voltage exceeds a threshold. This dynamic adaptation resolves the contradiction between efficiency and ripple suppression.
Solution Approach 2:
The patent implements feedback control by monitoring the output ripple voltage with a detection circuit and using this information to adjust the switching frequency. When the ripple voltage exceeds a predetermined threshold, the feedback signal triggers an increase in switching frequency to suppress the ripple, thereby resolving the contradiction between maintaining low frequency for efficiency and suppressing ripple when it becomes excessive.
2Object-generated harmful factors
If the on-time of the MOS transistor is reduced to suppress ripple voltage, then output ripple voltage is reduced, but power conversion efficiency deteriorates
Solution Approach 1:
The patent makes the on-time parameter dynamic by adjusting it based on detected ripple voltage levels. Rather than maintaining a fixed reduced on-time that would continuously degrade efficiency, the system dynamically increases on-time when ripple suppression is not needed (light load conditions), thereby improving efficiency while still suppressing ripple when necessary.
Solution Approach 2:
The patent changes the operating parameters (switching frequency and on-time) based on detected conditions. When ripple voltage is within acceptable limits, the system maintains longer on-time for efficiency; when ripple exceeds thresholds, the system changes parameters by reducing on-time and increasing frequency to suppress ripple, thus resolving the contradiction between these two parameters.
3Use of energy by moving object
If a conventional buck converter operates under light load conditions, then power consumption is reduced, but ripple voltage increases affecting output stability
Solution Approach 1:
The patent uses feedback control to monitor output voltage stability (ripple voltage) and automatically adjusts switching parameters in response. Under light load conditions, the system maintains low power consumption but activates feedback control to detect and suppress ripple voltage excursions, thereby maintaining both low power consumption and output stability simultaneously.
Solution Approach 2:
The patent applies dynamics by enabling the buck converter to adapt its switching behavior based on load conditions and detected ripple levels. Under light load, the system operates with longer on-times for efficiency but dynamically increases switching frequency when ripple becomes excessive, thus maintaining both low power consumption and output voltage stability across varying conditions.
Data Source
AI summary
A buck converter and a switching regulator capable of suppressing a ripple voltage under light load conditions. The buck converter has NMOS transistors QN2 and QN3 that are connected in series between input voltage VIN and the ground, inductor L1 that is connected to node SW where transistors QN2 and QN3 are connected, comparator COMP2 that compares respective voltages of node N1 and node N2 so as to decide on time of transistor QN2, and current detection circuit 100 that detects reverse current Ig flowing to the ground from inductor L1 via node SW and transistor QN3. When current detection circuit 100 detects reverse current Ig, voltage of node N1 of comparator COMP2 is reduced by variable circuit 110 in order to reduce the on time of transistor QN2.