High-Side Driver Gate-Stress Testing Without a Dedicated Test Pad

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Solution Overview

Problem

Existing high side driver circuits for buck regulators require a dedicated test pad for gate stress testing, which consumes die area and complicates the design, especially in split power MOS applications.

Innovation Solution

A high side driver circuit design that eliminates the need for a test pad by using a switch between the SBUCK and PHASE nodes, allowing for a gate-stress test mode that measures leakage current without a separate gate-stress pad, and can be adapted for multiple split power MOS transistors with a single switch.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If a dedicated test pad is used for gate stress testing, then gate stress testing can be performed, but die area is consumed and design is complicated

Engineering Contradiction:
Improvegate stress testing capabilityVSAvoiddie area
Core Design Contradiction:
ReliabilityVSArea of stationary object

Solution Approach 1:

The patent merges the gate stress testing function with the existing driver stage output. The driver stage output is directly coupled to the gate of the power MOS transistor, eliminating the need for a separate test pad. The same driver stage circuitry is used for both normal operation and gate stress testing by controlling the gate voltage through the existing output node.

Inventive Principle:
Principle #5Merging (Combining)

Solution Approach 2:

The driver stage is designed to serve multiple functions: it provides normal gate drive during operation and also enables gate stress testing when needed. By making the driver stage multi-functional, the patent eliminates the need for dedicated test pad structures while maintaining both operational and testing capabilities.

Inventive Principle:
Principle #6Universality (Multi-functionality)

2Reliability

If a dedicated test pad is used for gate stress testing, then gate stress testing can be performed, but device complexity increases

Engineering Contradiction:
Improvegate stress testing capabilityVSAvoiddriver stage complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent combines the gate stress testing functionality into the existing driver stage, merging two separate functions (normal operation and stress testing) into a single integrated circuit structure. This reduces device complexity by eliminating separate test pad connections and associated control circuitry.

Inventive Principle:
Principle #5Merging (Combining)

Solution Approach 2:

The driver stage is designed as a universal circuit that performs both normal gate driving and gate stress testing functions. This multi-functionality approach reduces overall device complexity by avoiding the need for separate dedicated test structures and their associated complexity.

Inventive Principle:
Principle #6Universality (Multi-functionality)

3Area of stationary object

If a switch is added between SBUCK and PHASE nodes for test mode, then gate stress testing becomes possible without test pad, but circuit complexity increases slightly

Engineering Contradiction:
Improvedie areaVSAvoidcircuit complexity
Core Design Contradiction:
Area of stationary objectVSDevice complexity

Solution Approach 1:

The patent extracts the gate stress testing capability from the external test pad structure and integrates it into the internal driver stage circuitry. By taking out the testing function from the periphery and embedding it in the core driver stage, the patent reduces die area while keeping the added complexity minimal and localized.

Inventive Principle:
Principle #2Taking out (Extraction)

Data Source

PatentUS8779804B2Gate-stress test circuit without test pad
Publication Date: 2014.07.15 STMICROELECTRONICS (SHENZHEN) R&D CO LTD
  • US8779804B2 patent drawing
  • US8779804B2 patent drawing
  • US8779804B2 patent drawing

AI summary

A high side driver circuit includes a driver stage having an input, an output, a first power terminal and a second power terminal, a transistor having a first power terminal, a second power terminal, and a control terminal coupled to the output of the driver stage, and a switch coupled between the second power terminal of the driver stage and the second power terminal of the transistor.