Interleaved Buck Gate Driver for SiC Switching Stress Control
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Solution Overview
Problem
Conventional gate drivers for wide band gap power devices, such as SiC devices, suffer from high switching losses due to high drain-source-voltage and drain-source-current peaks during switching, which are exacerbated by the use of high resistance gate resistors to mitigate these peaks.
Innovation Solution
A gate driving circuit utilizing an interleaved buck converter circuit with a pulse width modulation (PWM) control unit and feedback detection circuits to modulate gate voltage and current, dynamically controlling the gate voltage between positive and negative supply voltages during switching to suppress peak voltages and currents.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Stress or pressure
If high resistance gate resistors are used to reduce drain-source-voltage peak during switching off, then the drain-source-voltage peak is reduced, but switching loss increases
Solution Approach 1:
The gate driver dynamically adjusts the gate voltage waveform from a static high-resistance approach to a dynamic PWM-controlled waveform that adapts during the switching transition. The interleaved buck converter modulates the gate voltage in real-time to achieve both peak voltage reduction and lower switching losses by optimizing the voltage transition profile.
Solution Approach 2:
The invention changes the gate voltage parameter from a simple negative supply voltage level to a PWM-modulated waveform with variable duty cycle. This parameter change allows precise control over the gate voltage profile during switching, enabling simultaneous reduction of drain-source-voltage peak and switching loss by optimizing the voltage application timing and magnitude.
2Device complexity
If conventional push-pull circuits are used for gate driving, then the circuit topology is simple, but switching losses are high due to high drain-source-voltage peak
Solution Approach 1:
The gate driver is segmented into multiple push-pull circuits operating in parallel with interleaved switching sequences. This segmentation allows the total gate charging current to be distributed across multiple stages, enabling finer control over the voltage transition and reducing the peak drain-source voltage while maintaining a relatively simple overall topology.
Solution Approach 2:
The interleaved push-pull circuits operate with periodic switching sequences, where different circuits are activated in alternating phases. This periodic action creates a stepped or smoothed gate voltage waveform that reduces voltage peaks and minimizes switching losses compared to a single conventional push-pull circuit.
Data Source
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AI summary
The disclosure relates to a gate driving circuit for a power device, comprising an interleaved buck converter circuit (10), being connected to a gate (G) of the power device (200) to drive the gate (G); a pulse width modulation, PWM, control unit, being connected to the interleaved buck converter circuit (10); at least one feedback detection circuit, being connected between the power device (200) and the PWM control unit (20) and being configured for providing feedback information of the power device (200) to the PWM control unit (20); wherein the PWM control unit (20) is configured for modulating the interleaved buck converter circuit (10) based on the feedback information to control a gate voltage (VGS) or a gate current (IG) of the power device (200).