Buck Regulator Gate Drive Timing for Lower Switching Spikes
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Solution Overview
Problem
Buck regulators experience high emissions and reduced efficiency due to current spikes during switching activities, particularly at high frequencies, which are challenging to optimize across varying load currents and temperatures.
Innovation Solution
A current controlled buck regulator circuit with a half bridge configuration, utilizing a pair of drivers with different current capabilities, implements a variable delay in the switching process to smooth current transitions, optimizing the exchange of current between high and low side switches based on load current and temperature.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If switching frequency is increased to improve productivity, then output per unit time increases, but current spikes and emissions worsen
Solution Approach 1:
The patent applies dynamics by making the dead-time variable rather than fixed. The control unit adjusts the dead-time between switching signals based on real-time monitoring of current spikes, allowing the system to optimize the trade-off between switching frequency (productivity) and current spike suppression (emission reduction) under different operating conditions
Solution Approach 2:
The patent implements feedback by monitoring the current spikes generated during switching operations and using this information to dynamically adjust the dead-time parameter. The control unit receives feedback about emission levels and modifies the switching timing accordingly, creating a closed-loop system that balances productivity and emission control
2Loss of energy
If dead-time is reduced to improve efficiency, then power loss decreases, but current spikes and emissions increase
Solution Approach 1:
The patent makes the dead-time dynamic rather than static. By continuously adjusting the dead-time based on monitored current spike levels, the system can minimize dead-time (and thus power loss) when emissions are acceptable, while extending dead-time when current spikes become problematic, achieving an optimal balance between efficiency and emission control
Solution Approach 2:
The patent changes the dead-time parameter dynamically based on operating conditions. The control unit modifies this critical timing parameter in response to detected current spike levels, allowing the system to adapt the dead-time duration to minimize both power loss and emissions under varying load and temperature conditions
3Loss of energy
If rise time and fall time are reduced to improve efficiency, then switching losses decrease, but current spikes and emissions worsen
Solution Approach 1:
The patent applies preliminary action by introducing and optimizing the dead-time interval before switching transitions occur. This pre-switching timing adjustment prepares the circuit for the upcoming transition, allowing faster rise and fall times (improving efficiency) while the controlled dead-time prevents overlapping currents that would cause spikes and emissions
4Loss of energy
If current control is optimized for high load currents, then efficiency improves at high loads, but performance degrades at low loads and varying temperatures
Solution Approach 1:
The patent makes the dead-time parameter dynamic and adaptive to different operating conditions. Rather than being optimized for a single high-load condition, the control unit adjusts the dead-time based on real-time monitoring of current spikes across the entire load range and temperature variations, maintaining optimal efficiency and emission control under all operating conditions
Data Source
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AI summary
A current controlled buck regulator circuit (10; 100; 200), comprising a half bridge (20; 20') comprising a high side switch (21; 21a, 21b) and a low side switch (22), driven by a PWM signal (PWM_cmd) through respective drivers (41, 42; 141, 142), comprising a pair of drivers (41, 42; 141, 142) both coupled to a given switch among said high side switch (21; 21a, 21b) and low side switch (22) to supply selectively a first driving current (Ia) and a second driving current (Ib) to said given switch (21; 21a, 21b), enabling selectively said first (Ia) and/or second (Ib) driving current to supply a current switching on said given switch (21; 21a, 21b), the value of an ON current (HS_I) passing through said given switch (21; 21a, 21b) at the switch-on depending on which of said first (Ia) and/or second (Ib) driving current is enabled, a timing arrangement (141', 142'; 41s', 41b', 42') being configured during the switch-on of said switch (21; 21a, 21b), to enable said first (Ia) and/or second (Ib) driving current so that in said given switch (21; 21a, 21b) passes an ON current (IHSon) with a first value , then after a delay time enabling said first and/or second driving current so that in said given switch (21; 21a, 21b) passes an ON current (IHSon) with a second value greater than said first value.