Buck Converter MOSFET Layout for Snapback and On-Resistance Balance
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Solution Overview
Problem
Power management integrated circuits (PMICs) face challenges in maintaining snapback breakdown voltage while minimizing specific on-resistance, leading to potential issues like burnt failure and electrical overstress.
Innovation Solution
The implementation of a power management integrated circuit with a buck converter design that includes a first and second metal oxide semiconductor field effect transistor (MOSFET) with specific impurity region configurations, such as segmented second impurity regions in the source regions, to enhance snapback breakdown voltage and prevent excessive on-resistance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If impurity regions are added to source regions to increase snapback breakdown voltage, then reliability is improved, but specific on-resistance increases
Solution Approach 1:
The source region is divided into multiple segment regions (first, second, third segment regions) with different impurity concentrations and positions. This segmentation allows different portions of the source region to serve different functions: some segments provide snapback breakdown voltage enhancement while others minimize resistance increase, thereby resolving the technical contradiction between reliability and on-resistance.
Solution Approach 2:
Different impurity regions are positioned at specific locations within the source region based on local requirements. The first impurity region is positioned to enhance snapback breakdown voltage where needed, while the second and third impurity regions are positioned to control on-resistance. This local differentiation allows the source region to simultaneously achieve high reliability and low on-resistance.
2Power
If switching regulators are used to provide high driving voltage and power efficiency, then power management performance is improved, but vulnerability to electrical overstress and burnt failure increases
Solution Approach 1:
Impurity regions are pre-configured in the source regions of the MOSFETs within the switching regulator before operation. These impurity regions create a protective effect by enhancing snapback breakdown voltage, which cushions the device against electrical overstress and burnt failure that may occur during high-power switching operations, thereby improving endurance while maintaining power efficiency.
Data Source
AI summary
A power management integrated circuit includes a buck converter that includes a first metal oxide semiconductor field effect transistor (MOSFET) having a first conductivity type and a second MOSFET having a second conductivity type. The first MOSFET includes transistor sets that are two-dimensionally arranged. Each transistor set includes source regions, drain regions, and gate electrodes between the source regions and the drain regions. Each source region and each drain region includes an impurity region having the first conductivity type, and each source region further includes segment regions having the second conductivity type. A first source region is spaced apart from a second source region in a first direction, and a number of the segment regions in the first source region is different from a number of the segment regions in the second source region.