Buck Converter MOSFET Layout for Snapback and On-Resistance
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Solution Overview
Problem
Power management integrated circuits (PMICs) face challenges in maintaining snapback breakdown voltage while preventing an increase in specific on-resistance, which can lead to issues like burnt failure and electrical overstress.
Innovation Solution
The PMIC incorporates a buck converter with a first metal oxide semiconductor field effect transistor (MOSFET) and a second MOSFET, featuring a two-dimensional arrangement of transistor sets with source and drain regions having impurity regions of different conductivity types, and segment regions to manage voltage and resistance effectively.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If segment regions are added to source regions to prevent snapback breakdown voltage drop, then reliability is improved, but specific on-resistance increases
Solution Approach 1:
The patent applies local quality by differentiating the number of segment regions across different source regions based on their positional characteristics. Specifically, source regions closer to the center of the transistor set have more segment regions than those at the periphery. This localized differentiation optimizes the distribution of segment regions to prevent snapback breakdown voltage drop in critical areas while minimizing the overall increase in specific on-resistance, thus resolving the technical contradiction between reliability improvement and resistance control.
2Manufacturing precision
If segment regions are uniformly distributed in source regions, then manufacturing precision is improved, but endurance deteriorates due to snapback breakdown voltage drop
Solution Approach 1:
The patent employs asymmetry by deliberately creating an non-uniform distribution of segment regions across source regions. Instead of uniform distribution, the number of segment regions varies according to the position of each source region within the transistor set, with central source regions having more segments than peripheral ones. This asymmetric distribution strategy enhances endurance by preventing snapback breakdown voltage drop in high-stress central areas while maintaining manufacturability through a systematic design rule.
3Duration of action of stationary object
If the number of segment regions varies by source region position, then endurance is improved, but device complexity increases
Solution Approach 1:
The patent applies segmentation by dividing each source region into multiple segment regions separated by insulating films. This segmentation approach allows the device to achieve enhanced endurance through varied segment region counts in different positions while maintaining a modular structure that simplifies the overall design and manufacturing process. The segmented architecture enables flexible configuration without significantly increasing device complexity.
Data Source
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AI summary
A power management integrated circuit includes a buck converter that includes a first metal oxide semiconductor field effect transistor (MOSFET) having a first conductivity type and a second MOSFET having a second conductivity type. The first MOSFET includes transistor sets that are two-dimensionally arranged. Each transistor set includes source regions, drain regions, and gate electrodes between the source regions and the drain regions. Each source region and each drain region includes an impurity region having the first conductivity type, and each source region further includes segment regions having the second conductivity type. A first source region is spaced apart from a second source region in a first direction, and a number of the segment regions in the first source region is different from a number of the segment regions in the second source region.