Buck Regulator Error Feedback Loop Suppresses LC Filter Peaking
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Solution Overview
Problem
Buck regulators in audio applications experience undesirable peaking in the output voltage when audio signals near the resonance frequency are injected into the external LC filter, which is not effectively suppressed by existing technologies.
Innovation Solution
A modified buck regulator circuit with an internal error feedback loop that includes a pulse-width modulator, a switch, a filter, an integrator, a subtractor, and an adder to generate and adjust an error feedback signal, which is used to suppress voltage peaks at the resonance frequency of the filter.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If an external LC filter is used in the buck regulator, then high-frequency noise is filtered out effectively, but voltage peaking occurs at the resonance frequency when audio signals are injected
Solution Approach 1:
The patent introduces an internal error feedback loop that samples the output voltage, compares it with a reference voltage, and feeds the error signal back to the PWM controller. This feedback mechanism detects voltage peaking at the resonance frequency and adjusts the switching duty cycle to suppress the peaking, thereby maintaining stable output voltage while preserving the filtering performance of the external LC filter.
Solution Approach 2:
The patent dynamically adjusts the switching frequency of the buck regulator based on the detected output voltage conditions. When voltage peaking is detected at the resonance frequency, the switching frequency is modified to move away from the resonant condition, thereby suppressing the peaking effect while maintaining effective filtering of high-frequency noise through the LC filter.
2Loss of energy
If the buck regulator operates in Class D mode for high audio input signals, then high efficiency is achieved, but mode switching causes peaking in the LC filter output
Solution Approach 1:
The internal error feedback loop continuously monitors the output voltage during mode switching transitions between Class D and PFM operation. When peaking is detected during mode switching, the feedback signal adjusts the PWM duty cycle to compensate for the transient peaking effect, thereby maintaining energy efficiency while suppressing harmful voltage peaks during transition periods.
Solution Approach 2:
The feedback mechanism anticipates mode switching events by detecting changes in operating conditions and pre-adjusts the switching parameters to minimize peaking effects during the transition from Class D to PFM mode or vice versa, thereby maintaining efficiency while preventing harmful transients.
3Device complexity
If conventional buck regulator design is used, then simple circuit structure is maintained, but peaking suppression and settling time reduction are insufficient
Solution Approach 1:
The patent adds an internal error feedback loop that includes minimal additional components: a voltage sampling network, an error amplifier, and a feedback signal injection point in the PWM control path. This feedback mechanism provides effective peaking suppression and improved settling time while adding only modest circuit complexity, maintaining the simplicity of the overall buck regulator design.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The internal error feedback loop effectively dampens voltage peaking in the output signal, reducing the settling time of the regulator and ensuring a stable output voltage, as demonstrated by the closed loop response diagrams and bode graphs showing increased suppression of peaking with varying gain values.
Implementation Method 1
a pulse-width modulator (PWM) operable to generate a pulse-width modulated signal
Implementation Method 2
a filter, having a resonance frequency, the filter coupled to the switch for filtering out high frequency noise from the pulsed output DC signal
Implementation Method 3
an integrator operable to compare the pulsed output DC signal with a reference voltage signal and generate an error signal
Implementation Method 4
a subtractor operable to subtract the reference voltage signal from the filtered output signal to generate an error feedback signal
Implementation Method 5
an adder operable to add the error feedback signal to the error signal for input to the pulse-width modulator in order to substantially suppress voltage peaks in the filtered output signal at the frequency near the resonance frequency of the filter
Data Source
AI summary
Disclosed are systems and methods for suppressing voltage peaking in a buck regulator. In one aspect, a buck regulator comprises: a pulse-width modulator (PWM) that generates a pulsed signal; a switch operable to selectively connect the regulator to a DC power supply in response to the pulsed signal and output a pulsed output DC signal; a filter for filtering out high frequency noise from the pulsed output DC signal and generating a regulated output signal; an integrator for comparing the pulsed output DC signal with a reference voltage signal and generating an error signal for input to the PWM; a subtractor operable to subtract the reference voltage signal from the filtered output signal to generate an error feedback signal; and an adder operable to add the error feedback signal to the error signal for input to the pulse-width modulator in order to suppress voltage peaks in the filtered output signal.