Buck Converter Valley Current Control With Adaptive High Impedance
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Solution Overview
Problem
Conventional buck converters face challenges in maintaining efficient voltage regulation and stability, particularly at lower load currents, where they may transition to pulse frequency mode (PFM) and require adaptive control strategies to manage high impedance states and slope-compensated valley current commands without needing negative power supply voltages.
Innovation Solution
The implementation of a controller that dynamically adjusts the high side transistor on-time and introduces an adaptive high impedance state during each switching cycle, using a slope-compensated valley command current and an offset current to maintain stability and regulate output voltage across varying load conditions, without requiring a negative power supply.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of energy
If conventional buck converters operate at lower load currents, then they may transition to pulse frequency mode (PFM) to improve efficiency, but they require adaptive control strategies and negative power supply voltages to manage high impedance states and slope-compensated valley current commands
Solution Approach 1:
The patent changes the operating parameters by eliminating the need for negative power supply voltages and simplifying the control strategy. The controller maintains stable operation at low load currents by using a simplified valley current mode control that does not require complex adaptive strategies or negative voltage supplies, thus improving efficiency without proportionally increasing complexity
Solution Approach 2:
The patent extracts and removes the requirement for negative power supply voltages from the system. By redesigning the control approach, the invention eliminates this additional component requirement, thereby maintaining low-load efficiency benefits while reducing overall system complexity and component count
2Loss of energy
If the converter operates in pulse frequency mode (PFM) at low load currents, then efficiency improves, but stability and voltage regulation become more difficult to maintain
Solution Approach 1:
The patent implements feedback control through the valley current mode control mechanism that monitors inductor current and adjusts transistor switching accordingly. This feedback ensures stable voltage regulation during PFM operation by continuously adapting the switching cycle length and transistor on-times based on actual operating conditions, maintaining reliability while operating efficiently at low loads
Solution Approach 2:
The patent employs dynamic control by continuously adapting the switching cycle length and transistor on-times based on load conditions. The controller dynamically adjusts operating parameters to maintain stable voltage regulation across varying load conditions, ensuring reliability while benefiting from PFM efficiency at low currents
3Reliability
If the switching cycle length and transistor on-times are dynamically adjusted, then voltage regulation stability improves, but control complexity increases
Solution Approach 1:
The patent uses periodic clock pulses to control the switching cycles. The clock pulse triggers the high side transistor to turn off and the low side transistor to turn on, creating a regular periodic switching pattern. This periodic action provides stable voltage regulation through predictable, rhythmic control while keeping the controller design relatively simple through the use of standard clock circuitry
Data Source
AI summary
A switching regulator includes a first transistor having a control input and the first transistor is coupled to an input voltage terminal. The regulator includes a second transistor having a control input. The second transistor is coupled to the first transistor at a switch terminal and to a ground terminal. The regulator also includes a controller coupled to the control inputs of the first and second transistor. The controller configured is configured to cause both the first and second transistors to be off concurrently during each of multiple switching cycles for an adaptive high impedance state. The length of time of the adaptive high impedance state is inversely related to current output by the switching regulator.