Bucketed Allocator Tag Storage With Zero-Redundancy Metadata

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Solution Overview

Problem

Existing memory tagging techniques for buffer overflows and use-after-free vulnerabilities introduce substantial memory and performance overhead due to redundant tag storage and poor cache locality, complicating hardware design.

Innovation Solution

Implementing zero-redundancy tag storage by placing tags inline with allocations in bucketed memory regions, using metadata such as tags at the beginning or end of each slot, and supporting instruction set architecture to recognize allocation slot sizes, with additional instructions for tag management and access control.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If traditional memory tagging techniques are used to detect buffer overflows and use-after-free vulnerabilities, then memory safety is improved, but memory overhead and performance overhead increase substantially due to redundant tag storage

Engineering Contradiction:
Improvememory safetyVSAvoidmemory overhead
Core Design Contradiction:
ReliabilityVSQuantity of substance

Solution Approach 1:

The patent merges the tag storage with the allocation metadata by placing tags at the beginning or end of each allocation slot in bucketed memory regions. This combining of tag and metadata eliminates redundant tag storage while maintaining memory safety detection capabilities.

Inventive Principle:
Principle #5Merging (Combining)

Solution Approach 2:

The patent applies tagging selectively to bucketed memory regions where allocations are grouped by size, rather than uniformly tagging all memory. This localized approach reduces overall memory overhead while maintaining security for critical allocations.

Inventive Principle:
Principle #3Local quality

2Reliability

If traditional memory tagging techniques are used, then memory safety is improved, but performance overhead increases due to poor cache locality

Engineering Contradiction:
Improvememory safetyVSAvoidperformance
Core Design Contradiction:
ReliabilityVSProductivity

Solution Approach 1:

By merging tags with allocation metadata in the same memory location, the patent ensures that tag accesses occur alongside natural metadata accesses during allocation and deallocation operations. This co-location improves cache locality and reduces performance overhead.

Inventive Principle:
Principle #5Merging (Combining)

Solution Approach 2:

The patent performs tag validation as part of the natural allocation and deallocation workflow in bucketed memory regions, rather than as separate operations. This integration ensures tags are checked at the appropriate moments without adding performance overhead.

Inventive Principle:
Principle #10Preliminary action

3Reliability

If traditional memory tagging techniques are used, then memory safety is improved, but hardware complexity increases complicating hardware design

Engineering Contradiction:
Improvememory safetyVSAvoidhardware complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent applies the tagging mechanism specifically to bucketed memory regions where allocations are managed in slots with metadata, rather than implementing a universal tagging system. This targeted approach simplifies hardware design by avoiding redundant tagging infrastructure for other memory types.

Inventive Principle:
Principle #3Local quality

Solution Approach 2:

The patent uses existing allocation metadata structures in bucketed memory regions to store tags, making the metadata serve dual purposes: tracking allocation state and storing security tags. This multi-functionality eliminates the need for separate tag storage hardware.

Inventive Principle:
Principle #6Universality (Multi-functionality)

Data Source

PatentUS12504891B2Zero-redundancy tag storage for bucketed allocators
Publication Date: 2025.12.23 INTEL CORP
  • US12504891B2 patent drawing
  • US12504891B2 patent drawing
  • US12504891B2 patent drawing

AI summary

Methods and apparatus relating to zero-redundancy tag storage for bucketed allocators are described. In some embodiments, memory stores a memory page. The memory page includes a metadata page and a plurality of slots. The metadata page includes information corresponding to the plurality of slots. Decode circuitry decodes an instruction that includes a source operand. Execution circuitry executes the decoded instruction according to the source operand to load a first tag for a first slot of the plurality of slots in response to a memory access request directed at the first slot of the plurality of slots. The memory access request is allowed to proceed in response to a match between the first tag and a second tag of a pointer of the memory access request. The memory page stores a separate tag in proximity to each of the plurality of slots. Other embodiments are also disclosed and claimed.