Bias-Controlled Buffer Circuit for Overvoltage and Leakage Protection
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Solution Overview
Problem
Low-voltage devices in buffer circuits are susceptible to damage from overvoltage and undesired leakage currents due to the shrinking transistor size and increased operation voltage in CMOS technology, leading to gate-oxide breakdown and hot-carrier degradation.
Innovation Solution
A buffer circuit design incorporating a pre-driver, voltage-detection and bias circuit, and high-voltage tolerance output/input buffers, which generate bias voltages to manage conduction states of PMOS and NMOS transistors, preventing overvoltage damage and leakage currents by adjusting bias voltages and turning off circuits as needed.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If the transistor size is scaled down to reduce chip area and increase operation speed, then the gate oxide becomes thinner and the maximum allowable voltage decreases, but the operation voltage remains high causing overvoltage damage to transistors
Solution Approach 1:
The patent dynamically adjusts the bias voltage applied to transistor gates based on detected voltage levels. When high voltage is detected, the bias circuit modifies gate voltages to ensure the voltage differential across any transistor remains within safe limits, preventing overvoltage damage while allowing the transistor to operate at higher speeds
Solution Approach 2:
The patent introduces a bias circuit as an intermediary component between the power supply and transistor gates. This bias circuit acts as a mediator that conditions the voltage before it reaches the transistors, ensuring safe operating conditions while enabling high-speed operation
2Use of energy by moving object
If the operation voltage is higher than the nominal voltage of transistors, then the buffer circuit can operate at higher voltages, but the voltage across transistor terminals exceeds the nominal voltage causing gate-oxide breakdown and hot-carrier degradation
Solution Approach 1:
The patent dynamically adjusts bias voltages applied to transistor gates based on detected voltage levels. When high voltage operation is detected, the bias circuit modifies gate-source and gate-drain voltage differentials to remain within safe limits, preventing gate-oxide breakdown and hot-carrier degradation while enabling high-voltage operation
Solution Approach 2:
The patent applies bias voltages to transistor gates in advance before the actual signal passes through. This preliminary action ensures that the voltage across transistor terminals is pre-conditioned to safe levels, preventing damage before it can occur
3Adaptability or versatility
If the voltage of node 140 is higher than the voltage of power supply node VDD, then the buffer circuit can handle higher input voltages, but an undesirable leakage current flows from node 140 to VDD through the parasitic diode of PMOS transistor
Solution Approach 1:
The patent introduces a bias circuit as an intermediary that conditions the voltage at the PMOS gate. By applying an appropriate bias voltage, the circuit prevents the parasitic diode from becoming forward-biased, thereby blocking leakage current while maintaining the ability to handle higher input voltages
Data Source
AI summary
The present invention discloses a buffer circuit including: a pre-driver providing a first, a second, a third and a fourth driving signals according to the voltages of voltage nodes and control signals; a voltage-detection and bias circuit providing bias voltages for an output buffer and an input buffer according to the voltages of the voltage nodes and the third driving signal; the output buffer determining conduction states of the transistors of the output buffer according to the voltages of the voltage nodes, the first and the second driving signals, and the bias voltages, and thereby outputting an output signal to a signal pad; and the input buffer determining the conduction states of the transistors of the input buffer according to the voltage of the signal pad, the voltages of the voltage nodes, the fourth driving signals, and the several bias voltages, and thereby generating an input signal.