Buffer Circuit Branch Timing to Reduce Shoot-Through Current

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Solution Overview

Problem

Magnetic field sensors in low power applications experience increased power dissipation due to shoot-through currents caused by slow signal transitions in buffer circuits, which are undesirable in battery-operated devices.

Innovation Solution

A buffer circuit design using symmetrical circuit branches with starved inverter and signal recovery stages generates intermediate signals with delayed and faster edges, combined in a break before make fashion to reduce shoot-through current and power dissipation.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Power

If a buffer circuit is used to generate digital signals, then the signal can drive digital portions of the sensor, but slow signal transitions cause shoot-through current and increased power dissipation

Engineering Contradiction:
Improvepower dissipationVSAvoidsignal transition speed
Core Design Contradiction:
PowerVSSpeed

Solution Approach 1:

The buffer circuit is divided into two separate symmetrical branches (first branch and second branch), each handling opposite transitions. The first branch generates a first intermediate signal with delayed falling edges, while the second branch generates a second intermediate signal with delayed rising edges. This segmentation allows independent optimization of each branch to eliminate shoot-through current while maintaining fast transition speeds.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The circuit introduces intermediate signals with pre-delayed edges before combining them in the output stage. The first intermediate signal has falling edges delayed relative to the digital input signal, and the second intermediate signal has rising edges delayed. This preliminary delay action ensures that transitions are staged to prevent overlap, eliminating shoot-through current before it can occur in the final output.

Inventive Principle:
Principle #10Preliminary action

2Use of energy by moving object

If portions of the device are activated for short awake time intervals to reduce power consumption, then low power operation is achieved, but shoot-through current during transitions still increases power dissipation

Engineering Contradiction:
Improvepower consumptionVSAvoidenergy lost to shoot-through current
Core Design Contradiction:
Use of energy by moving objectVSLoss of energy

Solution Approach 1:

The circuit converts the potentially harmful shoot-through current into a beneficial design feature by using symmetrical branches with deliberately delayed edges. The first branch delays falling edges and the second branch delays rising edges, ensuring that when one branch is transitioning, the other is stable. This transforms what would be energy-wasting simultaneous transitions into a controlled sequence that eliminates shoot-through current while maintaining low power operation during awake intervals.

Inventive Principle:
Principle #22Blessing in disguise (Convert harm into benefit)

3Loss of energy

If the buffer output signal has faster edges to reduce shoot-through current, then power dissipation is reduced, but the signal is delayed relative to the input signal

Engineering Contradiction:
Improvepower dissipation from shoot-through currentVSAvoidsignal delay
Core Design Contradiction:
Loss of energyVSLoss of time

Solution Approach 1:

Different delay characteristics are applied locally to different aspects of the signal. The falling edges of the first intermediate signal are delayed relative to the digital input signal, while the rising edges are substantially coincident. Conversely, the second intermediate signal has delayed rising edges but coincident falling edges. This local differentiation of delay properties allows the output to have fast transitions overall while accepting minimal delay, optimizing both power efficiency and timing.

Inventive Principle:
Principle #3Local quality

Data Source

PatentUS12483244B2Buffer with reduced shoot-through current
Publication Date: 2025.11.25 ALLEGRO MICROSYSTEMS LLC
  • US12483244B2 patent drawing
  • US12483244B2 patent drawing
  • US12483244B2 patent drawing

AI summary

A buffer includes a first branch to receive a digital input signal and generate a first intermediate signal having falling edges that are delayed and faster than rising edges of the digital input signal and rising edges that are substantially coincident with falling edges of the digital input signal and a second branch to receive the digital input signal and generate a second intermediate signal having rising edges that are delayed and faster than falling edges of the digital input signal and falling edges that are substantially coincident with rising edges of the digital input signal. An output stage has a first input to receive the first intermediate signal, a second input to receive the second intermediate signal, and an output at which a buffer output signal is provided as a delayed version of the digital input signal having faster rising and falling edges than the digital input signal.