Buffer Cache Pre-emption via Availability Tracking

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Solution Overview

Problem

The existing multi-page allocation process in NAS systems is inefficient and non-deterministic, often resulting in thrashing and delayed application performance due to blind pre-emption of buffer cache pages, which complicates the allocation of contiguous memory pages.

Innovation Solution

Each frame table entry is augmented with a link to a buffer cache descriptor, allowing the allocation process to intelligently evaluate the availability of buffer cache pages for pre-emption, thereby ensuring contiguous page allocation and reducing thrashing.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If blind pre-emption of buffer cache pages is used to allocate contiguous memory pages, then allocation speed is improved, but system stability deteriorates due to thrashing

Engineering Contradiction:
Improveallocation speedVSAvoidsystem stability
Core Design Contradiction:
ProductivityVSReliability

Solution Approach 1:

The patent applies preliminary action by pre-evaluating buffer cache pages and marking them with availability indicators before allocation is needed. The buffer cache descriptor contains pre-computed information about whether a page is currently in use or available for pre-emption, allowing the allocation process to quickly identify suitable pages without causing thrashing.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The patent implements feedback by using buffer cache descriptors that provide real-time status information about buffer cache pages. The allocation process queries this feedback information to determine which pages can be safely pre-empted, creating a closed-loop system that adapts to current memory usage conditions and avoids thrashing.

Inventive Principle:
Principle #23Feedback

2Ease of operation

If the free list is used to allocate pages, then allocation simplicity is improved, but memory contiguity deteriorates

Engineering Contradiction:
Improveallocation simplicityVSAvoidmemory contiguity
Core Design Contradiction:
Ease of operationVSShape

Solution Approach 1:

The patent introduces an intermediary mechanism - the frame table with availability indicators - that bridges the free list and the buffer cache. This intermediary structure allows the allocation process to maintain the simplicity of free list operations while simultaneously ensuring memory contiguity by selecting from pre-evaluated contiguous buffer cache pages.

Inventive Principle:
Principle #24Intermediary (Mediator)

3Productivity

If buffer cache pages are pre-empted without evaluation, then allocation efficiency is improved, but performance deteriorates due to thrashing

Engineering Contradiction:
Improveallocation efficiencyVSAvoidthrashing
Core Design Contradiction:
ProductivityVSObject-generated harmful factors

Solution Approach 1:

The patent applies preliminary action by pre-evaluating buffer cache pages and marking them with availability indicators before allocation is needed. The buffer cache descriptor contains pre-computed information about whether a page is currently in use or available for pre-emption, allowing the allocation process to quickly identify suitable pages without causing thrashing.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The patent implements feedback by using buffer cache descriptors that provide real-time status information about buffer cache pages. The allocation process queries this feedback information to determine which pages can be safely pre-empted, creating a closed-loop system that adapts to current memory usage conditions and avoids thrashing.

Inventive Principle:
Principle #23Feedback

Data Source

PatentUS7509461B1Method and apparatus for intelligent buffer cache pre-emption
Publication Date: 2009.03.24 EMC IP HLDG CO LLC
  • US7509461B1 patent drawing
  • US7509461B1 patent drawing
  • US7509461B1 patent drawing

AI summary

The present invention augments each entry in a memory frame table to include information associated with the availability of any page that is buffer cache allocated. The availability information may include, for example, a link to a buffer cache descriptor associated with a buffer cache allocated page. Alternatively, the availability information may include a use status of the buffer cache allocated page. During a consecutive multi-page allocation process, pages which are buffer cache allocated are checked for availability. Should a buffer cache allocated page be available for use, it is intelligently pre-empted by the allocation process. By providing a mechanism to readily determine buffer cache page availability, a multi-page allocation process with increased efficiency may make intelligent decisions about the appropriateness of buffer cache page pre-emption.