Buffer Memory Calculation Circuit for Processor Data Latency
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Solution Overview
Problem
In computationally intensive data processing methods, processors with multiple cores often face bottlenecks due to limited memory bandwidth, leading to delays in data access and processing.
Innovation Solution
The implementation of a processor with a calculation circuit in buffer memory that can perform predetermined computational operations independently of processor cores, using Pim instructions to execute operations directly in memory.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of operation
If computational operations are performed using processor cores with instructions, then the operations can be flexibly controlled, but data traffic between processor cores and buffer memory increases causing latency
Solution Approach 1:
The processor is segmented into distinct functional units: processor cores for control and buffer memories with integrated calculation circuits for execution. This segmentation allows operations to be performed where data resides, eliminating the need for data to travel to processor cores while maintaining operational flexibility through the control unit's instruction management.
Solution Approach 2:
A control unit acts as an intermediary between the processor cores and buffer memories, managing the division of computational tasks. It determines which operations are executed in buffer memories versus processor cores, optimizing the balance between operational flexibility and data access efficiency without requiring constant data transfer.
2Productivity
If multiple processor cores are used for computationally intensive processing, then processing speed increases, but limited memory bandwidth creates bottlenecks
Solution Approach 1:
The calculation circuit is merged with the buffer memory, creating a unified computational unit. This allows multiple processor cores to access buffer memories for execution without competing for memory bandwidth, as the calculation occurs in-place within the buffer memory itself, effectively eliminating the memory bandwidth bottleneck while maintaining high processing speed.
3Productivity
If data is transferred between main memory and processor cores, then computational operations can be performed, but the data transfer causes delays in processing
Solution Approach 1:
Data is pre-loaded into buffer memories where calculation circuits are integrated, performing computational operations before the data would need to be transferred to processor cores. This preliminary execution in the buffer memory eliminates subsequent data transfer delays while maintaining computational throughput, as results can be directly used or written back without additional transfers.
Data Source
AI summary
A processor for performing a predetermined computational operation in which one or multiple data element(s) is/are used to determine a result. The processor includes one or more processor core(s) and at least one buffer memory, connectable to a main memory, and if the main memory is connected, it is designed to access the main memory. Each processor core is designed to execute instructions. The at least one buffer memory includes a calculation circuit which is designed to perform the computational operation in response to an execution signal if the one or the multiple data element(s) is/are stored in the buffer memory, the result being stored in the buffer memory. The processor is designed to perform the computational operation optionally using one of the processor cores with the aid of the instructions or to perform it in the at least one buffer memory using the respective calculation circuit.