Output Buffer Calibration Circuit for High-Frequency Impedance Tuning

The patent applies preliminary action by performing impedance calibration adjustments across multiple calibration periods rather than requiring completion within a single period. The calibration circuit accumulates adjustment steps over successive calibration periods, allowing the impedance adjustment to progress toward the target value even when each individual calibration period is truncated by high external clock frequencies. This resolves the contradiction by preparing and executing calibration adjustments in advance and continuing them across multiple periods.

The patent applies continuity of useful action by making the calibration operation continuous across multiple calibration periods. Instead of discarding adjustment content when calibration is incomplete within one period, the circuit preserves and continues the adjustment process in subsequent periods. This ensures that the useful action of impedance calibration accumulates over time rather than being interrupted or reset, thereby achieving both high precision and efficient use of calibration opportunities.

The patent applies feedback by continuously monitoring the calibration progress and determining whether to discard adjustment content based on actual completion status rather than assuming failure. The calibration circuit evaluates whether the impedance adjustment has converged to the target value or is making sufficient progress, and only discards adjustments when genuine abnormalities are detected. This feedback mechanism allows the system to maintain high impedance accuracy even at high clock frequencies by preserving valid partial adjustment results.