Output Buffer Calibration Circuit for High-Clock Impedance Tuning

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Solution Overview

Problem

High-frequency external clocks limit the number of impedance adjustment steps in calibration operations for output buffers, often resulting in incomplete impedance adjustments and discarded adjustment content, making it difficult to achieve target impedance accuracy.

Innovation Solution

A calibration circuit with first and second replica buffers, a counter circuit, and latch circuits that allow impedance code fetching even if the impedance of the replica buffers does not reach a predetermined level within the calibration period, enabling continued calibration operations from a previous point and improving accuracy.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Speed

If the frequency of the external clock is increased to achieve high data transfer rates, then the data transfer rate is improved, but the number of adjusting steps executable during the calibration period decreases, making it difficult to complete impedance adjustment

Engineering Contradiction:

Improvedata transfer rateVSAvoidnumber of adjusting steps

Core Design Contradiction:

SpeedVSProductivity

Solution Approach 1:

The invention stores the impedance adjustment content in a storage circuit before the calibration period ends. This preliminary action preserves the adjustment results so they can be applied later, allowing the calibration to continue effectively even when the calibration period is too short to complete all adjusting steps at high clock frequencies.

Inventive Principle:

Principle #10Preliminary action

Solution Approach 2:

The invention enables continuous calibration across multiple calibration periods by storing adjustment content and applying it sequentially. Instead of discarding adjustment content when calibration doesn't complete within one period, the system maintains continuity by preserving and resuming calibration in subsequent periods, ensuring the impedance adjustment process can eventually complete regardless of clock frequency.

Inventive Principle:

Principle #20Continuity of useful action

2Speed

If the calibration period is shortened due to high external clock frequency, then the data transfer rate is improved, but the impedance adjustment cannot be completed within the calibration period, resulting in discarded adjustment content

Engineering Contradiction:

Improveexternal clock frequencyVSAvoidimpedance adjustment completion

Core Design Contradiction:

SpeedVSReliability

Solution Approach 1:

The storage circuit performs a preliminary action by saving the impedance adjustment content before the calibration period expires. This ensures that even if the adjustment isn't complete within the shortened calibration period, the progress is preserved and can be continued in the next calibration period, preventing loss of adjustment content.

Inventive Principle:

Principle #10Preliminary action

Solution Approach 2:

The end-determining circuit provides feedback about whether the impedance adjustment has completed within the calibration period. Based on this feedback, the system decides whether to apply the adjustment content immediately or store it for later application, ensuring reliable impedance adjustment completion regardless of clock frequency.

Inventive Principle:

Principle #23Feedback

3Device complexity

If the frequency-dividing number is increased to allow more adjusting steps, then the calibration period can accommodate more steps, but the number of adjusting steps per calibration period decreases

Engineering Contradiction:

Improvefrequency-dividing numberVSAvoidnumber of adjusting steps per calibration period

Core Design Contradiction:

Device complexityVSProductivity

Solution Approach 1:

Inventive Principle:

Principle #10Preliminary action

Data Source

PatentUS7656186B2Calibration circuit, semiconductor device including the same, and data processing system

Publication Date: 2010.02.02 LONGITUDE LICENSING LTD

AI summary

A calibration circuit includes: replica buffers; an up-down counter that changes impedance codes of the replica buffers; latch circuits each holding the impedance codes; an end-determining circuit that activates the latch circuits in response to a completion of impedance adjustments of the replica buffers; and a 32 tCK cycle counter that forcibly activates the latch circuits in response to a lapse of a predetermined period since issuance of the calibration command. Thereby, even when the adjustment is not completed during one calibration period, a subsequent calibration operation can be executed from a previous point.