Buffering Capacitor De-Charging Control for Power Factor
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing energy buffering arrangements, such as those using thyristors, struggle to precisely control the amplitude and timing of de-charging currents, leading to inefficient energy management and power factor issues.
Innovation Solution
An energy buffering arrangement comprising a buffer capacitor circuit with a larger capacitance than a smoothing capacitor circuit, along with a current source circuit, trigger circuit, and latch circuit, which defines and stabilizes the de-charging current amplitude, improving control over de-charging and enhancing power factor.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If a thyristor-based valley-fill-in circuit is used, then the circuit structure is simple, but the control precision of de-charging current amplitude is poor
Solution Approach 1:
The patent changes the control parameter from voltage-based (thyristor) to current-based (current source circuit). The current source circuit actively regulates the de-charging current amplitude by controlling the gate voltage of the MOSFET, allowing precise adjustment of current parameters rather than relying on passive voltage breakdown characteristics.
Solution Approach 2:
The patent replaces the thyristor-based mechanical/electromagnetic control system with an electronic current source control system. The current source circuit uses electronic components (MOSFET, operational amplifier, resistors) to provide precise electronic control of the de-charging current, substituting the less precise thyristor firing mechanism.
2Reliability
If a thyristor is used for de-charging control, then the device complexity is low, but the power factor is poor
Solution Approach 1:
The patent implements a feedback mechanism where the current source circuit continuously monitors and adjusts the de-charging current amplitude. The operational amplifier compares the actual current with the reference voltage and adjusts the MOSFET gate voltage accordingly, providing closed-loop control that optimizes power factor by ensuring controlled energy transfer back to the grid.
3Quantity of substance
If the buffer capacitor circuit has larger capacitance, then the energy buffering capability is improved, but the leakage current increases
Solution Approach 1:
The patent makes the de-charging process dynamic and controllable rather than passive. The current source circuit actively manages the discharge timing and current amplitude, allowing the system to optimize the balance between maintaining adequate buffer capacitance for energy storage and controlling the discharge rate to minimize leakage losses.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The proposed solution allows for precise control of de-charging currents and improved power factor, outperforming traditional thyristor-based systems by ensuring better-defined de-charging and reduced leakage currents.
Implementation Method 1
a buffer capacitor circuit comprising one or more buffer capacitors
Implementation Method 2
a second circuit comprising a current source circuit for defining an amplitude of a de-charging current
Data Source
AI summary
Arrangements (1) for buffering energy comprise buffer capacitor circuits (10) with one or more buffer capacitors (11), first circuits (20) for guiding charging currents for charging the buffer capacitor circuits (10), and second circuits (30) with current source circuits (31-34) for defining amplitudes of de-charging currents for de-charging the buffer capacitor circuits (10), to better control the de-charging of the buffer capacitor circuits (10). The second circuits (30) may further comprise trigger circuits (51-53) for bringing the current source circuits (31-34) into activated modes, and latch circuits (61-63) for latching the current source circuits (31-34). The arrangements (1) may further comprise smoothing capacitor circuits (40) with one or more smoothing capacitors (41). The buffer capacitor circuits (10) may be coupled serially to the first circuits (20), and the first and second circuits (20, 30) may be coupled in parallel to each other.