Output Buffer Circuit With Pre-Discharged Capacitor Feedback
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Solution Overview
Problem
Conventional output buffer circuits experience delays and degradation in slew rate due to charge storage in capacitors, leading to timing issues and reduced signal quality when suppressing overshoot and undershoot.
Innovation Solution
The proposed output buffer circuit design includes a capacitor with switches that manage charge storage, ensuring the capacitor is discharged before state changes, using a driving circuit to control the output transistor and switches to synchronize with input signal levels, thereby preventing delay and degradation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If capacitor elements are provided between output terminal and gate terminals to suppress overshoot and undershoot, then signal quality is improved, but output signal delay and slew rate degradation occur due to charge storage in capacitors
Solution Approach 1:
The patent applies preliminary action by discharging the capacitor elements before the output transistor switches states. Specifically, before the output transistor turns ON, the capacitor is discharged through a discharge path, ensuring it is ready to suppress overshoot/undershoot without causing delay. This preliminary discharge action eliminates the time required to discharge stored charge during critical switching moments.
Solution Approach 2:
The patent implements dynamics by making the capacitor discharge path controllable and time-dependent. Switches are used to dynamically connect or disconnect the discharge path based on the operating state of the output transistor. This dynamic control allows the capacitor to be discharged at appropriate moments, optimizing both overshoot suppression and signal transition speed.
2Stability of the object's composition
If capacitor elements are used to suppress overshoot and undershoot, then signal stability is improved, but slew rate degradation occurs due to charge discharge time requirements
Solution Approach 1:
The capacitor is discharged in advance before the output transistor switches, so that when the switching event occurs, no charge discharge time is required during the critical transition period. This preliminary action ensures the capacitor is in a neutral state ready to suppress overshoot/undershoot without affecting the slew rate.
Solution Approach 2:
The discharge path is designed to be continuously available or frequently activated, ensuring the capacitor maintains its charge in a controlled manner. This continuous management of charge ensures the capacitor is always ready to provide overshoot/undershoot suppression without interrupting the signal transition continuity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This design minimizes delay and slew rate degradation while effectively suppressing overshoot and undershoot, ensuring rapid signal transitions and improved output signal quality.
Implementation Method 1
capacitor elements 19 and 20, each having a first terminal connected to output terminal 22... because capacitor element 19 is provided between output terminal 22 and node N1, overshoot generated when output signal B1 changes to 'H' level is fed back through capacitor element 19 to node N1
Data Source
AI summary
An output buffer circuit, which minimizes or prevents output delay of output signal and degradation of slew rate while suppressing overshoot and undershoot, is provided. In a first time period when an input signal to a gate of an N-channel output transistor changes from ‘L’ level to ‘H’ level, the gate is connected to an output terminal through a capacitor element so that the overshoot is suppressed. In addition, the output buffer circuit stores negligible electrical charge in the capacitor element prior to the first time period, which results in minimal delay in outputting a buffered signal and degradation of slew rate while suppressing undershoot when the input signal changes from ‘H’ level to ‘L’ level in the first time period.