Configurable Buffer Chains for Multiphase Clock Duty Cycle Correction
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Solution Overview
Problem
In high-speed chip-to-chip communication systems, existing Phase-Locked Loop (PLL) and Delay-Locked Loop (DLL) technologies face challenges in maintaining stable and accurately phased receiver clock signals due to variations among ring oscillator elements, leading to undesirable duty cycle variations and skew between output clock phases.
Innovation Solution
A configurable clock buffer chain is introduced, allowing adjustment of clock duty cycle and overall delay by modifying the rise and fall times of signals between buffer stages, combined with a measurement subsystem to directly measure and correct clock duty cycle and inter-phase skew, ensuring clean and accurately timed multiphase clock signals.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If PLL or DLL is used to generate multiple local clock phases, then the receiver can achieve accurate sampling timing, but variations among ring oscillator elements cause duty cycle variations and skew between output clock phases
Solution Approach 1:
The patent implements a feedback mechanism where the measurement subsystem continuously monitors duty cycle and skew of the generated clock phases, and the control logic adjusts the buffer chain parameters accordingly to maintain uniform duty cycles and minimize skew, resolving the contradiction between achieving accurate sampling timing and maintaining duty cycle uniformity
Solution Approach 2:
The patent replaces the traditional mechanical/physical ring oscillator-based clock generation with a configurable buffer chain system that uses electronic control to generate and adjust clock phases, allowing digital control and measurement to compensate for variations and achieve both accurate timing and uniform duty cycles
2Productivity
If ring oscillator elements are used to produce multiple clock phases, then the system can provide the required clock signals, but element variations induce periodic clock variations and skew
Solution Approach 1:
The patent introduces configurable buffer chains as intermediary elements between the clock source and the measurement/distribution points. These buffer chains act as mediators that can be adjusted to compensate for variations in ring oscillator elements, maintaining clock phase stability while preserving the ability to generate multiple clock phases
Solution Approach 2:
The measurement subsystem provides continuous feedback on clock phase skew and duty cycle variations, enabling the control logic to adjust the buffer chain parameters in real-time, thereby maintaining reliable and stable clock signals despite variations in the underlying oscillator elements
3Manufacturing precision
If clock duty cycle and delay are adjusted by modifying rise and fall times, then accurate multiphase clock signals can be achieved, but the system complexity increases
Solution Approach 1:
The patent designs the configurable buffer chain to perform multiple functions: clock signal buffering, duty cycle adjustment, delay compensation, and skew correction. By making the buffer chain multi-functional, the patent reduces the need for separate dedicated circuits for each function, thereby managing system complexity while achieving accurate clock phase control
Data Source
AI summary
Methods and systems are described for generating, at a plurality of delay stages of a local oscillator, a plurality of phases of a local oscillator signal, generating a loop error signal based on a comparison of one or more phases of the local oscillator signal to one or more phases of a received reference clock, generating a plurality of phase-specific quadrature error signals, each phase-specific quadrature error signal associated with a respective phase of the plurality of phases of the local oscillator signal, each phase-specific quadrature error signal based on a comparison of the respective phase to two or more other phases of the local oscillator signal, and adjusting each delay stage according to a corresponding phase-specific quadrature error signal of the plurality of phase-specific quadrature error signals and the loop error signal.