Buffer Chain for Scan Chain Synchronization
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Solution Overview
Problem
State retention power gating in electronic devices faces challenges when scan chains of different lengths are used, as dummy clock cycles or elements are required to synchronize them, complicating clock tree design and increasing chip area.
Innovation Solution
The implementation of a buffer chain that compensates for the length difference between scan chains, allowing them to operate synchronously by shifting data through a buffer chain of appropriate length, thereby simplifying the clock tree design and reducing area costs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Stability of the object's composition
If dummy clock cycles are introduced to synchronize scan chains of different lengths, then synchronous operation is achieved, but clock tree design becomes complicated
Solution Approach 1:
The patent introduces a buffer chain as an intermediary component between scan chains of different lengths. This buffer chain acts as a mediator that absorbs the length difference, allowing all scan chains to be clocked synchronously without requiring complex dummy clock cycle insertion logic in the clock tree. The buffer chain receives data from shorter scan chains and outputs it in synchronization with longer scan chains, thereby simplifying the clock tree design while maintaining synchronous operation.
2Stability of the object's composition
If dummy stateful elements are added to equalize scan chain lengths, then synchronous operation is achieved, but chip area increases
Solution Approach 1:
The buffer chain serves as a compact intermediary structure that achieves length equalization without requiring additional dummy stateful elements in each scan chain. Instead of adding elements throughout the scan chain network, the buffer chain consolidates the length compensation function in a dedicated buffer structure, thereby achieving synchronous operation with minimal area overhead compared to distributing dummy elements across multiple scan chains.
Solution Approach 2:
The patent shifts the length equalization function from the horizontal dimension (adding elements within scan chains) to the vertical dimension (introducing a separate buffer chain structure). This dimensional change allows the system to handle scan chain length differences by adding a buffer stage rather than expanding the scan chain elements themselves, effectively reducing the area impact of length equalization.
3Area of stationary object
If scan chains of different lengths are operated without synchronization, then chip area is reduced, but state retention accuracy deteriorates
Solution Approach 1:
The buffer chain acts as a synchronization intermediary that preserves state retention accuracy without requiring all scan chains to be of equal length. By introducing this buffer mediator, the system can operate scan chains of different lengths in parallel while maintaining accurate state capture and restoration, thus preserving reliability while avoiding the area penalty of adding dummy elements to equalize all chain lengths.
Data Source
AI summary
An electronic device may include a set of two or more scan chains and a buffer chain. Each of the scan chains includes a sequence of stateful elements connected in series, and each of the scan chains is arranged to hold a string having a length identical to the length of the respective scan chain. The strings of the scan chains are shifted in parallel from the scan chains into the memory unit and back from the memory unit into the respective scan chains. The store operation and the restore operation each include at least N0 elementary downstream shift operations. The set of scan chains includes a short chain and a detour chain, and the short chain has a length N1 which is shorter than N0. The set of scan chains further includes a buffer chain. The output end of the short chain is coupled to an input end of the buffer chain. The buffer chain is provided at least partly by the detour chain.