Buffer Chip Command Fixing for High-Capacity Memory Packages
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Solution Overview
Problem
Existing computer systems face challenges in increasing memory capacity while maintaining low latency and high bandwidth due to issues such as latency and bandwidth limitations, making it difficult to add memory effectively.
Innovation Solution
A semiconductor package design incorporating a buffer chip that includes various circuits to manage chip select signals, command addresses, and control signals, allowing for efficient communication between a memory controller and multiple memory chips, reducing loading and cost through wire bonding instead of through-silicon vias.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If memory capacity is increased by adding more memory chips, then the amount of data that can be processed increases, but latency increases and bandwidth decreases
Solution Approach 1:
A buffer chip is introduced as an intermediary component between the memory controller and multiple memory chips. The buffer chip receives command address signals from the memory controller, decodes them, and distributes appropriate commands to specific memory chips. This intermediary structure enables parallel access to multiple memory chips, reducing latency and increasing bandwidth while maintaining high memory capacity.
2Reliability
If command address signals are continuously transmitted to all memory chips, then all chips remain responsive, but current consumption increases
Solution Approach 1:
The buffer chip decodes command address signals and generates differentiated chip select signals for each memory chip. Only the selected memory chip corresponding to the decoded address receives the active command signal, while other memory chips remain in a low-power standby state. This local differentiation of signal distribution reduces overall current consumption while maintaining the ability to quickly activate any specific memory chip when needed.
3Speed
If through-silicon vias are used to connect memory chips, then signal transmission speed increases, but manufacturing complexity and cost increase
Solution Approach 1:
The patent extracts the high-speed signal transmission function from the through-silicon via approach and implements it through a buffer chip with decoding logic. Instead of physically penetrating silicon layers with complex vias, the buffer chip uses electrical signal routing and decoding to achieve fast access to multiple memory chips. This extraction simplifies manufacturing while maintaining signal transmission speed through efficient logic design.
Data Source
AI summary
A buffer chip includes: a chip select signal reception circuit configured to receive chip select signals transmitted from a memory controller; a command address reception circuit configured to receive command address signals transmitted from the memory controller; a chip select signal transmission circuit configured to transmit the chip select signals to a plurality of memory chips; a command address transmission circuit configured to transmit the command address signals to the plurality of memory chips; and a command address fixing circuit configured to fix levels of at least one of the command address signals transmitted by the command address transmission circuit when the chip select signals are deactivated for a predetermined time or more.