Buffer Chip Data Format Conversion for Memory Efficiency

Resolve Bottlenecks,
Find Innovative Solutions
Generate Solutions

Solution Overview

Problem

In high-performance computer architectures, there is a trade-off between data transmission efficiency and computation precision, as existing solutions that reduce data transmission delay by converting data formats within the accelerated computation unit occupy additional computing resources, thereby decreasing computation efficiency.

Innovation Solution

A data format conversion apparatus and method implemented on a buffer chip, which performs data format conversion and storage address mapping without occupying additional computing resources of the accelerated computation unit, ensuring precision and improving efficiency by converting data formats during transmission between the CPU's main memory and the accelerated computation unit's device memory.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Measurement precision

If high-precision data format is used in data transmission process, then computation precision is satisfied, but the amount of data transmission is increased and data transmission delay is increased

Engineering Contradiction:
Improvecomputation precisionVSAvoiddata transmission delay
Core Design Contradiction:
Measurement precisionVSLoss of time

Solution Approach 1:

The patent changes the data precision parameter dynamically: low-precision data format is used for transmission to reduce delay, while high-precision data format is used for computation to ensure accuracy. The buffer chip automatically converts between these formats, allowing the system to optimize both transmission speed and computation precision without manual intervention.

Inventive Principle:
Principle #35Parameter changes

2Loss of time

If two data format conversion units are added into the accelerated computation unit, then the amount of data transmission is reduced, but computing resources and computation time are additionally occupied and efficiency of accelerated computation is decreased

Engineering Contradiction:
Improvedata transmission delayVSAvoidcomputation efficiency
Core Design Contradiction:
Loss of timeVSProductivity

Solution Approach 1:

The patent extracts the data format conversion function from the accelerated computation unit and places it in a separate buffer chip. This extraction allows the conversion operations to be performed in parallel with computation operations, eliminating the conflict where conversion units would occupy computing resources. The buffer chip handles format conversion independently while the accelerated computation unit focuses solely on computation tasks.

Inventive Principle:
Principle #2Taking out (Extraction)

3Quantity of substance

If data format conversion is performed within the accelerated computation unit, then data transmission volume is reduced, but additional computing resources are occupied

Engineering Contradiction:
Improvedata transmission volumeVSAvoidcomputing resources occupation
Core Design Contradiction:
Quantity of substanceVSDevice complexity

Solution Approach 1:

The buffer chip serves as an intermediary component between the CPU and the accelerated computation unit. It performs data format conversion as a mediating function, translating between low-precision transmission data and high-precision computation data. This intermediary approach reduces data transmission volume while avoiding the need to occupy additional computing resources within the accelerated computation unit itself.

Inventive Principle:
Principle #24Intermediary (Mediator)

Data Source

PatentUS10402119B2Data format conversion apparatus and method and buffer chip
Publication Date: 2019.09.03 HUAWEI TECH CO LTD
  • US10402119B2 patent drawing
  • US10402119B2 patent drawing
  • US10402119B2 patent drawing

AI summary

The present disclosure provides a data format conversion apparatus and method, and a buffer chip. The data format conversion apparatus is disposed on the buffer chip in a memory; a control module is disposed for sending a control instruction to a conversion module when obtaining a data copy command; and a conversion module is disposed for completing data format conversion and storage address mapping on to-be-converted data according to the received control instruction. In this way, a prior-art problem of additionally occupying computing resources and computation time of an accelerated computation unit due to a data format conversion unit disposed in the accelerated computation unit is avoided, the amount of data transmission between a main memory and a device memory is reduced without additionally occupying computing resources, and the computation precision is ensured while the computation efficiency is improved.