Buffer Chip Delay Clock Generation for 3D Memory Timing
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Solution Overview
Problem
In three-dimensional (3D) memory devices, the increasing number of stacked layers leads to varying data transmission clocks for each memory cell, resulting in inefficiencies when using uniform data clocks, requiring significant time and resources for compensation operations.
Innovation Solution
A memory system with a buffer chip acting as an interface circuit, which generates and stores delay clock signals to optimize data signal compensation, including a delay clock generation chain, registers, and a sampler to adjust strobe and data signals based on reference clock signals.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If uniform data clocks are used in 3D memory devices with increasing stacked layers, then device complexity is reduced, but manufacturing precision deteriorates due to varying data transmission clocks for each memory cell
Solution Approach 1:
The patent segments the clock signal generation into multiple independent delay chains (first delay chain and second delay chain), each capable of providing different delay amounts. This allows different memory cells to receive customized clock signals with appropriate delays, resolving the timing precision issue while maintaining a modular clock distribution architecture.
Solution Approach 2:
The patent implements dynamic clock signal adjustment by allowing the selection of different delay amounts from the delay chains based on the specific memory cell requirements. The clock signals are dynamically adjusted to compensate for varying data transmission characteristics across different stacked layers, enabling precise timing control without requiring a completely complex custom clock system for each cell.
2Manufacturing precision
If optimized data clock duty is applied to each memory cell, then manufacturing precision is improved, but device complexity increases due to the need for multiple delay chains and registers
Solution Approach 1:
The patent creates a universal clock signal generation structure where the first and second delay chains can serve multiple memory cells with different timing requirements. The delay chains are designed to provide a range of delay amounts that can be selectively applied to different memory cells, making the circuit multi-functional rather than requiring dedicated custom circuits for each cell.
Solution Approach 2:
The patent optimizes clock signal parameters by adjusting the delay amounts in the delay chains to achieve the desired clock duty cycle for each memory cell. By changing the delay parameter, the system can optimize the clock duty to match the specific data transmission characteristics of different memory cells without fundamentally changing the circuit architecture.
3Manufacturing precision
If compensation operations are performed on data clocks for 3D memory devices, then manufacturing precision is improved, but loss of time increases due to the significant time consumed in compensation operations
Solution Approach 1:
The patent performs preliminary timing compensation by pre-calculating and pre-adjusting the clock signal delays using the delay chains before data transmission begins. The delay amounts are determined in advance based on the memory cell characteristics, and the clock signals are pre-adjusted to the appropriate delays, eliminating the need for time-consuming compensation operations during actual data transmission.
Solution Approach 2:
The patent replaces iterative compensation operations with a direct delay-based timing adjustment mechanism. Instead of performing repeated compensation operations to correct timing errors, the system uses carefully designed delay chains to directly establish the correct timing relationship between clock signals and data transmission, significantly reducing the time required for timing adjustment.
Data Source
AI summary
Provided is a memory system including a memory device including a plurality of non-volatile memories, each of the plurality of non-volatile memories being electrically connected to a buffer chip, and a memory controller electrically connected to the buffer chip and configured to transmit a reference clock signal used in correction of a data signal, wherein the buffer chip includes a delay clock generation chain configured to generate a first delay clock signal or a second delay clock signal from the reference clock signal, a first register configured to store the first delay clock signal, and a second register configured to store the second delay clock signal, and wherein the buffer chip is configured to perform compensation on a strobe signal of the data signal based on the first delay clock signal, and perform compensation on the data signal based on the second delay clock signal.