Buffer Chip Loopback Circuit for High-Capacity Memory Packages
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Solution Overview
Problem
As the demand for increased memory capacity in computer systems, such as data centers and servers, grows due to applications like artificial intelligence and big data, existing methods face challenges in adding memory while maintaining low latency and high bandwidth, leading to increased loading and manufacturing costs.
Innovation Solution
A semiconductor package design that includes a buffer chip and multiple memory chips stacked on a package substrate, with the buffer chip acting as an intermediary to communicate with both the memory controller and memory chips, reducing loading and manufacturing costs by using wire bonding instead of through-silicon vias, and incorporating a loopback circuit for signal testing and a leakage test circuit to identify defects.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If memory capacity is increased to meet growing data processing demands, then memory capacity is improved, but latency increases and bandwidth decreases
Solution Approach 1:
The memory system is segmented into multiple independent memory chips (first memory chip, second memory chip, etc.) that can be accessed simultaneously. This segmentation allows parallel data operations, increasing effective bandwidth and reducing latency while providing large total capacity through the aggregation of multiple smaller memory units.
2Quantity of substance
If memory capacity is increased by adding more memory chips, then memory capacity is improved, but manufacturing cost increases
Solution Approach 1:
The buffer chip is designed with multi-functionality to interface with multiple different types of memory chips (first memory chip, second memory chip, third memory chip with different configurations). This universal interface design allows the same buffer chip to work with various memory chip types and capacities, reducing overall manufacturing costs through component standardization and reusability.
3Quantity of substance
If memory capacity is increased by stacking memory chips, then memory capacity is improved, but device complexity increases
Solution Approach 1:
The memory package employs a nested stacking architecture where multiple memory chips are vertically stacked on the buffer chip in layers. The first memory chip is stacked on the buffer chip, the second memory chip is stacked on the first memory chip, and so on, creating a compact three-dimensional structure that increases capacity while managing complexity through hierarchical organization.
Solution Approach 2:
The buffer chip serves as an intermediary between the memory controller and the stacked memory chips. It manages signal routing, data buffering, and coordination between multiple memory chips, simplifying the overall system complexity by providing a centralized control point that abstracts the complexity of managing multiple stacked memory devices.
4Ease of manufacture
If wire bonding is used instead of through-silicon vias, then manufacturing cost is reduced, but connection reliability may be affected
Solution Approach 1:
The wire bonding process creates multiple redundant electrical connections between the buffer chip and memory chips through the package substrate. This copying of connection paths provides alternative signal routes and enhances reliability through redundancy, compensating for the inherently lower reliability of wire bonding compared to through-silicon via connections.
Data Source
AI summary
A buffer chip includes: an external control signal interface configured to receive control signals transmitted from a memory controller; an internal control signal interface configured to transmit the control signals to a plurality of memory chips; an external data interface configured to transmit and receive (transmit/receive) data to and from (to/from) the memory controller; an internal data interface configured to transmit/receive the data to/from the plurality of memory chips; and a loopback circuit configured to be activated in a loopback mode to receive the control signals transmitted by the internal control signal interface, and transmits the control signals to the external data interface.