Buffer Chip Multi-Level Signaling for Legacy NAND Interfaces
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing memory systems face challenges in implementing high-speed communication in low-speed NAND memory interfaces without increasing design costs or complexity by adopting PAM4 signaling, which requires complicated hardware and software changes.
Innovation Solution
A memory system and method that utilize a buffer chip with a receiver circuit and multiplexer to recover bitstreams from composite multi-level signals, aligning data signal edges, and output them to a memory controller, enabling high-speed communication without altering existing hardware or software configurations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If PAM4 signaling is adopted for high-speed data transfer, then data transfer rate is improved, but hardware configuration complexity and design costs increase
Solution Approach 1:
A buffer chip is introduced as an intermediary component between the memory controller and NAND flash memory. The buffer chip receives data signals from the memory device, combines multiple low-speed signals into a single high-speed multi-level signal, and transmits it to the memory controller. This intermediary approach enables high-speed communication without requiring the memory controller or memory device to be redesigned for PAM4 signaling.
Solution Approach 2:
The system is divided into three functional segments: the memory device (outputting low-speed signals), the buffer chip (combining and converting signals), and the memory controller (receiving high-speed signals). This segmentation allows each component to maintain its original simple interface while the buffer chip handles the complexity of multi-level signal generation and conversion.
2Productivity
If PAM4 signaling is implemented, then throughput is improved, but software changes and design costs increase
Solution Approach 1:
The buffer chip serves as a mediator that isolates the complexity of PAM4 signaling from the memory controller and memory device. It receives simple low-speed signals from the memory device, converts them to high-speed multi-level signals, and transmits them to the memory controller. This eliminates the need for software changes in the memory controller or memory device while achieving high throughput.
Solution Approach 2:
Instead of making permanent, complex changes to the memory controller and memory device hardware/software, the solution uses a separate buffer chip that can be independently designed and replaced. This approach is more cost-effective as it avoids expensive redesigns of existing components while still achieving the desired throughput improvement.
3Speed
If multi-level signaling is used in legacy interface, then data transfer rate is improved, but signal alignment complexity increases
Solution Approach 1:
The buffer chip performs preliminary signal alignment and combination before transmitting to the memory controller. It receives data signals from multiple memory devices, aligns their edges in time, combines them into a single multi-level signal, and outputs it to the memory controller. This preliminary action eliminates the need for complex alignment mechanisms in the memory controller or memory devices.
Data Source
AI summary
A memory system includes a first memory device outputting a first data signal through a first data pin, a second memory device outputting a second data signal through a second data pin, a memory controller controlling the first and second memory devices, a buffer chip connected between the memory controller and each of the first and second memory devices, and a first signal line connecting the buffer chip to each of the first and second data pins. The buffer chip comprises a receiver circuit receiving a multi-level signal from the first signal line, comparing the multi-level signal with multiple reference voltage levels, and output multiple determination values, a multiplexer recovering a bitstream from the multi-level signal based on the multiple determination values, and outputting the bitstream to the memory controller, and a control circuit aligning an edge of the first data signal with an edge of the second data signal.