Buffer Chip Per-Pin Training for High-Speed Storage Signal Alignment
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Solution Overview
Problem
Existing storage devices face challenges in aligning communication signals between non-volatile memory and controllers at high operating frequencies, leading to potential communication errors and reduced performance due to signal skew and duty mismatch.
Innovation Solution
A method involving a buffer chip with a delay circuit, sampler, comparator, and counter module is used to perform per-pin training, where random data signals and data strobe signals are transmitted and delayed to determine a target delay, ensuring accurate phase alignment and duty cycle correction, thereby improving communication accuracy.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If communication within storage device is performed at high operating frequency, then communication speed is improved, but signal alignment accuracy deteriorates due to signal skew and duty mismatch
Solution Approach 1:
The patent performs per-pin training before normal communication operations to pre-align signal phases. The training process adjusts delay times for each pin in advance, ensuring that data signals and strobe signals are properly synchronized before high-speed communication begins, thus preventing signal alignment issues at high frequencies
Solution Approach 2:
The patent dynamically adjusts delay time parameters for each pin based on training results. By changing the delay time parameter, the system optimizes signal alignment for high-frequency operation, compensating for signal skew and duty mismatch that occur at higher speeds
2Measurement precision
If per-pin training is performed to align communication signals, then signal alignment accuracy is improved, but device complexity increases due to additional training circuits and procedures
Solution Approach 1:
The buffer chip performs self-training by autonomously adjusting its own delay circuits based on comparing sampled data with expected data patterns. This self-service approach eliminates the need for external training equipment or complex controller intervention, reducing overall system complexity while achieving accurate signal alignment
Solution Approach 2:
The patent introduces a buffer chip as an intermediary between the memory device and controller. This buffer chip contains the training circuits and delay adjustment mechanisms, isolating the complexity from the main communication path and allowing simpler memory devices and controllers to benefit from precise signal alignment
3Reliability
If delay circuits and training mechanisms are added to buffer chip, then communication accuracy is improved, but manufacturing cost increases
Solution Approach 1:
The buffer chip is designed to perform multiple functions: normal data buffering, per-pin training, delay adjustment, and signal alignment. By making the buffer chip multi-functional, the patent avoids adding separate dedicated training devices, thereby improving communication accuracy while controlling manufacturing costs through component consolidation
Data Source
AI summary
A storage device includes a buffer chip and a memory device. The memory device transmits a random data signal and a data strobe signal to the buffer chip based on a clock signal received from the buffer chip. The buffer chip includes a delay circuit that delays the data strobe signal by a delay time to generate a delayed data strobe signal, a sampler that receives the delayed data strobe signal from the delay circuit and samples the random data signal based on the delayed data strobe signal to generate sampled data, a comparator that compares internal data with the sampled data to generate a comparison result, and a counter module that receives the comparison result from the comparator and determines a target delay based on the comparison result. The buffer chip delays the delayed data strobe signal based on the target delay.