Buffer Chip Signal Remapping for Defective Memory Package Ranks
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Solution Overview
Problem
The increasing demand for memory in computer systems due to AI and big data applications is hindered by latency and bandwidth issues, making it difficult to effectively add memory while maintaining performance, especially when some memory chips in semiconductor packages become defective.
Innovation Solution
A semiconductor package design that includes a buffer chip capable of receiving and mapping system chip select signals, allowing it to generate and transmit memory chip select signals to multiple memory chips, even if some chips are defective, thereby enabling the package to function with failed memory chips by rearranging chip select signals and maintaining available ranks.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If memory chips are stacked in semiconductor packages to increase memory capacity, then memory capacity increases, but reliability deteriorates due to defective chips causing entire package failure
Solution Approach 1:
The patent segments the chip select signal control by introducing a buffer chip that independently manages select signals for each memory chip. The buffer chip includes individual select signal reception circuits, mapping circuits, and transmission circuits for each memory chip, allowing granular control and isolation of defective chips from the package operation.
Solution Approach 2:
The buffer chip acts as an intermediary between the memory controller and multiple memory chips. It receives chip select signals from the memory controller, maps them to appropriate memory chips using mapping circuits, and transmits the mapped signals. This intermediary layer enables defective memory chips to be bypassed while maintaining package functionality.
2Reliability
If through-silicon vias are used to connect memory chips, then connection reliability improves, but manufacturing complexity and cost increase
Solution Approach 1:
The patent extracts the complex through-silicon via connection requirement by positioning the buffer chip on the package substrate rather than stacking it with memory chips using TSVs. The buffer chip communicates with memory chips through wire bonding, eliminating the need for TSVs while maintaining functional reliability through the buffer's signal mapping capability.
3Device complexity
If wire bonding is used instead of through-silicon vias, then manufacturing cost and complexity decrease, but connection reliability and signal integrity may deteriorate
Solution Approach 1:
The buffer chip serves as an intermediary that compensates for the limitations of wire bonding. By positioning the buffer chip close to the memory chips and using it to manage select signals, the design maintains signal integrity despite using wire bonding technology, achieving a balance between manufacturing simplicity and reliability.
4Reliability
If all memory chips in a package must be functional for the package to operate, then reliability is maintained, but productivity decreases due to entire package discarding when one chip fails
Solution Approach 1:
The patent segments the control of each memory chip through the buffer chip's individual select signal circuits. This segmentation allows the memory controller to activate only functional memory chips by sending select signals that are mapped to working chips while bypassing defective ones, enabling partial package operation and improving manufacturing yield.
Solution Approach 2:
The patent changes the operational parameter from all-or-nothing package operation to selective chip operation. The buffer chip's mapping circuits dynamically adjust which memory chips receive select signals based on their functional status, transforming the package from a rigid system where all chips must work to a flexible system that can operate with partial chip functionality.
Data Source
AI summary
A buffer chip may include: a chip select signal reception circuit configured to receive system chip select signals transmitted from a memory controller; a chip select signal mapping circuit configured to generate memory chip select signals by mapping the system chip select signals by using failed memory chip information; and a chip select signal transmission circuit configured to transmit the memory chip select signals to a plurality of memory chips.