Buffer Chip Register-Write Arbitration Without Clock-Domain Crossing
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Solution Overview
Problem
Existing memory module command buffer chips face complexity and latency issues due to clock domain crossing and dependency on high-speed clocks for asynchronous arbitration of register writes across clock domains.
Innovation Solution
An integrated circuit chip with an arbitration circuit that uses meta-hardened flip-flop circuits to perform asynchronous arbitration of register writes across clock domains, prioritizing high-speed interface commands and operating independently of the high-speed clock.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If clock domain crossing is used for asynchronous arbitration across clock domains, then register writes can be arbitrated between high-speed and low-speed interfaces, but the circuit complexity and size increase
Solution Approach 1:
The patent extracts the arbitration function from the high-speed clock domain and implements it independently in the low-speed clock domain using meta-hardened flip-flops. This separation eliminates the need for clock domain crossing circuitry while maintaining arbitration capability between interfaces operating at different clock speeds.
Solution Approach 2:
The patent introduces meta-hardened flip-flops as intermediary elements that can store and transfer arbitration state across clock domain boundaries without requiring traditional clock domain crossing synchronization. These flip-flops act as a mediator between the high-speed interface arbitration logic and the low-speed interface execution.
2Adaptability or versatility
If clock domain crossing is used for asynchronous arbitration, then register writes can be coordinated across different clock domains, but latency increases
Solution Approach 1:
The patent performs arbitration decisions in advance within the low-speed clock domain before high-speed interface transactions are executed. By pre-arbitrating register write requests and storing the arbitration state in meta-hardened flip-flops, the system eliminates runtime latency associated with clock domain crossing during actual data transfers.
3Stability of the object's composition
If dependency on high-speed clock is maintained for arbitration, then arbitration logic can operate synchronously, but the low-speed interface cannot operate when the high-speed clock is unavailable
Solution Approach 1:
The patent segments the arbitration logic into independent clock domain operations. The high-speed interface arbitration and low-speed interface arbitration operate independently in their respective clock domains, allowing each interface to function autonomously without dependency on the other's clock signal availability.
Data Source
AI summary
A buffer chip includes a first interface to receive in-band register access commands from a host and a second interface to receive side-band register access commands from the host. The buffer chip further includes an arbitration circuit coupled to the first interface and to the second interface, wherein the arbitration circuit is to receive control signals from the first interface indicating a first pending register access command for the first interface, and wherein the arbitration circuit is to select the first pending register access command from concurrent pending register access commands from the first interface and the second interface using the control signals. In addition, the buffer chip includes a command buffer register coupled to the arbitration circuit, wherein the arbitration circuit to perform, on the command buffer register, a register access operation corresponding to the first pending register access command.