Buffer Chip Signal Routing for High-Capacity Memory Packages

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Solution Overview

Problem

Existing computer systems face challenges in increasing memory capacity while maintaining low latency and high bandwidth due to limitations in adding memory, particularly in applications utilizing artificial intelligence and big data.

Innovation Solution

A semiconductor package incorporating a buffer chip that performs buffering operations between a module controller and multiple memory chips, reducing loading and manufacturing costs by using wire bonding instead of through-silicon vias, and includes command decoders and setting circuits to manage chip select and command address signals for efficient memory chip settings.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Quantity of substance

If memory capacity is increased to meet AI and big data requirements, then the amount of data that can be processed increases, but latency increases and bandwidth decreases

Engineering Contradiction:

Improvememory capacityVSAvoidlatency

Core Design Contradiction:

Quantity of substanceVSLoss of time

Solution Approach 1:

The memory system is segmented into multiple independent memory chips (first memory chip, second memory chip, etc.) that can be accessed simultaneously. The buffer chip divides incoming memory access requests and distributes them to different memory chips, enabling parallel data processing and reducing overall access latency while maintaining high memory capacity.

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

A buffer chip is introduced as an intermediary component between the memory controller and multiple memory chips. The buffer chip manages control signals, coordinates access to different memory chips, and optimizes data flow, thereby reducing latency and maintaining high bandwidth while supporting increased memory capacity through parallel operations.

Inventive Principle:

Principle #24Intermediary (Mediator)

2Reliability

If through-silicon vias are used to connect memory chips, then connection reliability improves, but manufacturing cost and complexity increase

Engineering Contradiction:

Improveconnection reliabilityVSAvoidmanufacturing cost

Core Design Contradiction:

ReliabilityVSEase of manufacture

Solution Approach 1:

The patent replaces expensive through-silicon via technology with wire bonding, which uses relatively inexpensive wire bonds to achieve electrical connections between the buffer chip and memory chips. This substitution significantly reduces manufacturing cost and complexity while maintaining sufficient connection reliability for the application requirements.

Inventive Principle:

Principle #27Cheap short-living objects (Disposable)

Data Source

PatentUS12437803B2Buffer chip, semiconductor package including buffer chip and memory chip, operation method of buffer chip, and operation method of semiconductor package

Publication Date: 2025.10.07 SK HYNIX INC

AI summary

An operation method of a buffer chip may include receiving first control signals for setting a first memory chip; buffering the first control signals and transmitting the buffered signals to the first memory chip; storing a setting value of the first memory chip in response to the first control signals; receiving second control signals for setting a second memory chip; buffering the second control signals and transmitting the buffered second control signals to the second memory chip; storing a setting value of the second memory chip in response to the second control signals; receiving third control signals for applying the setting value of the first memory chip; buffering the third control signals and transmitting the buffered third control signals to the first memory chip; and applying the stored setting value of the first memory chip as a setting value of a buffer chip in response to the third control signals.