Buffer Chip Wire Bonding for Memory Stack Signal Integrity
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Solution Overview
Problem
In semiconductor packages, the increasing length of wire bonds due to stacked memory dies leads to deteriorated electrical characteristics, such as resistance and capacitance, affecting signal transmission efficiency.
Innovation Solution
The implementation of a buffer chip with strategically positioned die bond pads and wire bonds, where longer wire bonds connect to die bond pads closer to the memory die stack, and shorter wire bonds connect to die bond pads farther away, uniformizing electrical characteristics and improving connections.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If wire bonds are extended to connect distant memory dies in stacked configuration, then connectivity between dies is achieved, but electrical characteristics deteriorate due to increased length
Solution Approach 1:
A buffer chip is introduced as an intermediary component between the memory die stack and the package substrate. The buffer chip includes multiple die bond pads positioned at different locations (first set near the stack, second set farther away). Wire bonds connect from the memory die stack to the first set of die bond pads, and separate wire bonds connect from the package substrate to the second set of die bond pads. This intermediary buffer chip allows signal routing without requiring excessively long single wire bonds, thereby maintaining electrical characteristics while achieving connectivity.
Solution Approach 2:
The connection path is segmented into two separate wire bond paths instead of one long path. The first wire bonds connect the memory die stack to the first set of die bond pads on the buffer chip. The second wire bonds connect the package substrate to the second set of die bond pads on the buffer chip. This segmentation divides a potentially problematic long wire bond into two shorter segments, improving electrical characteristics while maintaining end-to-end connectivity.
2Reliability
If die bond pads are positioned close to the memory die stack, then wire bond length is reduced and electrical characteristics improve, but connection flexibility to package substrate is limited
Solution Approach 1:
The die bond pads are segmented into two distinct sets: a first set positioned close to the memory die stack for receiving wire bonds from the stack, and a second set positioned farther away for receiving wire bonds from the package substrate. This spatial segmentation allows each set of die bond pads to be optimized for its specific connection purpose, achieving both short wire bonds for the stack connection and flexible routing for the substrate connection.
Solution Approach 2:
The buffer chip provides an additional spatial dimension for connection routing. By positioning die bond pads at different locations on the buffer chip surface, the patent creates multiple connection pathways that can accommodate different routing requirements. The first set of die bond pads handles connections from the vertical stack dimension, while the second set handles connections from the horizontal substrate dimension, effectively utilizing spatial distribution to resolve the contradiction.
Data Source
AI summary
A buffer chip is wire-bonded to memory dies. A semiconductor package includes a semiconductor die stack, a first set of wire bonds connected to a first set of semiconductor dies, a second set of wire bonds connected to a second set of semiconductor dies, and the buffer chip. The second set of semiconductor dies are on the first set of semiconductor dies. The buffer chip includes a first set of die bond pads being close to the semiconductor die stack, and a second set of die bond pads being distant from the semiconductor die stack. The second set of wire bonds extends to the first set of die bond pads of the buffer chip, and the first set of wire bonds extends to the second set of die bond pads of the buffer chip.