Buffer Circuit Topology for Low Duty Cycle Distortion
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Solution Overview
Problem
Existing buffer circuits experience duty cycle distortion due to inconsistent time delays between rising and falling edges of output signals, which is exacerbated by variations in supply voltage, temperature, and manufacturing process, leading to reduced maximum operating frequency and increased distortion.
Innovation Solution
The improved buffer circuit decouples the charging and discharging current paths from the reference voltage, ensuring equal time delays between rising and falling edges by using complementary transistors with shared gate connections and diode-connected transistors to maintain equal current flow during logic transitions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional buffer circuits are used with CMOS inverters, then the circuit can provide basic signal buffering, but duty cycle distortion occurs due to inconsistent time delays between rising and falling edges
Solution Approach 1:
The patent applies asymmetry by using different transistor configurations for charging and discharging paths. Specifically, the charging path uses a PMOS transistor while the discharging path uses an NMOS transistor with different sizing ratios. This asymmetric design compensates for the inherent threshold voltage differences between PMOS and NMOS devices, ensuring that the time delays for rising and falling edges are equalized, thereby reducing duty cycle distortion.
Solution Approach 2:
The patent changes the physical parameters of the transistors, specifically the width-to-length ratios (W/L) of the PMOS and NMOS devices. By adjusting these geometric parameters, the patent optimizes the drive strength and switching characteristics of each transistor to achieve balanced rise and fall times. This parameter optimization directly addresses the time delay inconsistency problem.
2Adaptability or versatility
If supply voltage, temperature, or process variations occur, then the trip point of the buffer circuit deviates from ideal values, but this causes increased propagation delay differences between rising and falling edges
Solution Approach 1:
The patent implements a feedback mechanism through the cross-coupled transistor configuration where the output of each inverter stage feeds back to control the switching of transistors in the opposite path. This feedback ensures that when supply voltage, temperature, or process variations occur, the circuit automatically adjusts its operating point to maintain balanced rise and fall times, compensating for trip point deviations without increasing propagation delay differences.
3Speed
If additional CMOS inverter pairs are cascaded to increase propagation delay, then the buffer can handle higher frequency signals, but duty cycle distortion is exacerbated
Solution Approach 1:
The patent segments the buffer circuit into multiple identical stages, each designed with the balanced charging and discharging paths. By replicating the same symmetric structure across multiple stages, the patent ensures that each stage contributes equally to signal propagation while maintaining duty cycle integrity. This modular segmentation allows cascading for higher frequency operation without compounding duty cycle distortion.
Data Source
AI summary
An improved buffer circuit and method for minimizing (or altogether eliminating) duty cycle distortion between input and output signals of the buffer circuit are provided herein. In general, the improved buffer circuit essentially decouples the charging and discharging current paths of the buffer circuit from a reference voltage supplied to the buffer circuit. This ensures substantially equal time delays between rising and falling edges of the input and output signals, thereby decreasing duty cycle distortion and maintaining a maximum operating frequency of the buffer circuit, even when the reference voltage approaches a transistor threshold voltage. In addition, the improved method may include forwarding an input signal with an input duty cycle onto mutually connected gate terminals of a pair of pull-down transistors, and activating/inactivating at least one of the pair of pull-down transistors during logic high and logic low voltage values of the input duty cycle, respectively. In this manner, the method provides an output signal with an output duty cycle that is substantially equal to the input duty cycle.