Buffer Circuit Layout for Semiconductor Memory
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Solution Overview
Problem
The existing layout of buffer circuits in semiconductor memory devices, such as DRAM, results in increased area occupation by control circuits and elongated wiring lengths due to the alternation of unit buffer circuits, leading to inefficiencies in data transfer operations.
Innovation Solution
The proposed solution involves arranging ODD and EVEN buffer circuits with alternating unit buffer circuits in a specific layout that reduces the area occupied by control circuits and shortens wiring lengths by optimizing the positioning of unit buffer circuits and control circuits, allowing for more efficient data transfer through data buses.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If unit buffer circuits are alternately arrayed to simplify coupling to different buffer circuits, then coupling simplicity is improved, but control circuit area and wiring length increase
Solution Approach 1:
The buffer circuit is divided into multiple banks (first bank, second bank, third bank, fourth bank) with each bank containing unit buffer circuits. The control circuit is segmented to independently control each bank, allowing distributed control that reduces the area occupied by a single centralized control circuit while maintaining coupling simplicity.
Solution Approach 2:
Unit buffer circuits are arranged in a two-dimensional grid pattern across multiple banks rather than a simple linear alternation. This spatial distribution across different dimensions (banks arranged in rows and columns) reduces the wiring length from a centralized control point while preserving the alternating coupling structure.
2Ease of manufacture
If unit buffer circuits are alternately arrayed to simplify coupling, then coupling simplicity is improved, but wiring length increases
Solution Approach 1:
The control functionality is segmented across multiple control circuits, each responsible for specific banks. This segmentation allows each control circuit to be positioned closer to its controlled banks, reducing the wiring length while maintaining the alternating unit buffer circuit arrangement for coupling simplicity.
Solution Approach 2:
By organizing banks in a two-dimensional array and placing control circuits at strategic positions within this array, the wiring length is minimized through optimal spatial positioning. The alternating unit buffer circuits maintain coupling simplicity while the multi-dimensional layout reduces the distance signals must travel.
3Area of stationary object
If control circuit area is reduced through optimized layout, then area efficiency is improved, but data transfer efficiency may worsen
Solution Approach 1:
The control circuit is divided into multiple independent control units, each managing specific banks. This segmentation reduces the area of any single control circuit while enabling parallel data transfer operations across different banks, thereby maintaining or even improving overall data transfer efficiency.
Solution Approach 2:
Multiple control circuits work in parallel to manage different banks simultaneously. This merging of control functions across multiple units allows area reduction through distributed architecture while achieving high data transfer efficiency through parallel processing of multiple data streams.
Data Source
AI summary
Disclosed herein is an apparatus that includes: first and second memory groups including a plurality of first and second memory cells, respectively; a first buffer circuit configured to receive a plurality of first data bits from the first memory group; a second buffer circuit configured to receive a plurality of second data bits from the second memory group; a first error correction circuit configured to correct at least one of the plurality of first data bits; and a second error correction circuit configured to correct at least one of the plurality of second data bits. The first error correction circuit is arranged between the first and second buffer groups of the first buffer circuit in physical layout. The second error correction circuit is arranged between the third and fourth buffer groups of the second buffer circuit in physical layout.