Multi-Stage Buffer Circuit for Low-Offset Data Driving
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Display devices face issues with signal distortion due to load components in data lines and random offset caused by element mismatches in channel buffers, particularly near minimum or maximum voltage levels, and lack effective solutions for maintaining gain linearity.
Innovation Solution
A buffer design incorporating first and second output adjustment units with specific conductivity type transistors and power level connections to stabilize transistor operation across voltage ranges, ensuring consistent gain and offset characteristics.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a channel buffer is provided to amplify the data signal, then signal distortion due to load component is reduced, but random offset occurs due to element mismatch between buffer elements
Solution Approach 1:
The buffer is divided into multiple stages (first buffer stage, second buffer stage, third buffer stage) with distinct functions. The first stage provides voltage conversion, the second stage provides current amplification, and the third stage provides output buffering. This segmentation allows each stage to be optimized independently, reducing the impact of element mismatches on overall offset while maintaining signal amplification capability.
Solution Approach 2:
A current mirror circuit is introduced as an intermediary between the input stage and output stage. This current mirror acts as a mediator that transfers the amplified current signal while maintaining precise current relationships, thereby reducing the impact of direct voltage-level element mismatches on the final output offset.
2Measurement precision
If element size is increased to reduce random offset, then offset accuracy improves, but device area increases
Solution Approach 1:
The buffer function is segmented across three stages, allowing the use of smaller transistors in each stage compared to a single large transistor. The cumulative effect of multiple small-stage amplifications achieves the required overall gain without needing oversized elements, thus reducing total area while maintaining offset performance.
Solution Approach 2:
The invention changes the operating parameters of different stages - the first stage operates in voltage conversion mode, the second stage in high-gain current amplification mode, and the third stage in low-impedance output mode. This parameter optimization allows each stage to use appropriately sized elements for its function, minimizing total area while achieving required performance.
3Adaptability or versatility
If the buffer operates near minimum or maximum voltage levels, then dynamic range is maximized, but random offset increases significantly
Solution Approach 1:
The three-stage architecture distributes the voltage range handling across stages. The first stage handles voltage level conversion from input range to intermediate range, the second stage handles current amplification in a optimized voltage range, and the third stage handles output voltage restoration. This segmentation allows each stage to operate in its optimal voltage range, maintaining low offset even when the overall system operates across a wide dynamic range.
4Device complexity
If a conventional single-stage buffer is used, then device complexity is low, but gain linearity cannot be maintained
Solution Approach 1:
The buffer is segmented into three specialized stages, each optimized for its specific function (voltage conversion, current amplification, output buffering). This segmentation enables independent optimization of gain linearity in each stage through tailored circuit designs, achieving overall superior linearity performance compared to a single-stage buffer.
Solution Approach 2:
Different operating parameters are applied to each stage - the first stage uses voltage-mode operation with specific biasing for linear voltage conversion, the second stage uses current-mode operation with optimized tail currents for linear current amplification, and the third stage uses low-impedance output for linear voltage restoration. These parameter optimizations collectively achieve excellent gain linearity across the full operating range.
Data Source
AI summary
A buffer can include a first output adjustment unit configured to output a first signal, and a second output adjustment unit configured to output a second signal. The first output adjustment unit can include a first input stage configured to adjust a control current according to a difference between a first input voltage and a first output voltage, and a first output stage configured to output the first output voltage as the first signal. The first output voltage can be a voltage between a first level voltage and a second level voltage. The first input stage can be connected to a third power line that supplied a third level voltage. The first level voltage can be greater than the second level voltage. The second level voltage can be greater than the third level voltage.