Multi-Stage Buffer Circuit for Peak Current and Delay Reduction

Solution Overview

Problem

In electronic devices, as the number of buffer levels increases, time delay and power consumption also rise, leading to peak current/voltage exceeding the power source capacity, causing component damage and functional failure.

Innovation Solution

A buffer circuit with an odd number of cascaded buffers, including PMOS and NMOS transistors, where the transistors' driving capability is set to half or a quarter of the highest level buffer, reducing peak current and improving reaction speed.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Power

If the number of buffer levels is increased to improve driving capability, then the driving capability is improved, but time delay and power consumption increase sharply

Engineering Contradiction:

Improvedriving capabilityVSAvoidtime delay

Core Design Contradiction:

PowerVSLoss of time

Solution Approach 1:

The buffer circuit is divided into multiple levels with different driving capabilities. Lower levels have smaller driving capability while higher levels have greater driving capability. This segmentation allows the signal to be processed through multiple stages rather than requiring a single high-power buffer, reducing overall power consumption and time delay while achieving the required driving capability at the output.

Inventive Principle:

Principle #1Segmentation

2Power

If the number of buffer levels is increased to improve driving capability, then the driving capability is improved, but power consumption increases sharply

Engineering Contradiction:

Improvedriving capabilityVSAvoidpower consumption

Core Design Contradiction:

PowerVSUse of energy by moving object

Solution Approach 1:

The buffer circuit is divided into multiple levels with different driving capabilities. Lower levels have smaller driving capability while higher levels have greater driving capability. This segmentation allows the signal to be processed through multiple stages rather than requiring a single high-power buffer, reducing overall power consumption and time delay while achieving the required driving capability at the output.

Inventive Principle:

Principle #1Segmentation

3Power

If the driving capability of transistors is increased to handle peak current, then the driving capability is improved, but the peak current may surpass the capacity of the power source leading to component damage

Engineering Contradiction:

Improvedriving capabilityVSAvoidcomponent safety

Core Design Contradiction:

PowerVSReliability

Solution Approach 1:

The buffer circuit uses dynamic sizing where the driving capability of each buffer level is optimized for its specific function. The first level buffer has smaller driving capability for normal operation, while higher levels have progressively greater driving capability to handle peak currents. This dynamic allocation ensures that no single transistor is oversized, preventing peak current from surpassing power source capacity while maintaining component safety.

Inventive Principle:

Principle #15Dynamics

Data Source

PatentUS9979398B2Buffer circuit and electronic device using same

Publication Date: 2018.05.22 HERCULES MICROELECTRONICS CO LTD

AI summary

A buffer circuit includes a buffer group including an odd number of cascade buffers, where the buffers may be different from each other; a PMOS transistor and an NMOS transistor; where a source of the PMOS transistor is coupled to a power source, a drain thereof is connected to an output terminal of the buffer group, and a gate thereof is connected to an input terminal of the buffer group; a source of the NMOS transistor is coupled to ground, a drain thereof is connected to the output terminal of the buffer group, and a gate thereof is connected to the input terminal of the buffer group.