High-Voltage Buffer Circuit With Switched PMOS Backgate Control
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Solution Overview
Problem
PMOS transistors in tolerant buffer circuits face challenges in simultaneously meeting the requirements of having a breakdown voltage for the VDDH level and being gate-controlled with the VDDL level, leading to instability in outputting different high voltage levels.
Innovation Solution
Incorporating a switch circuit controlled by a high voltage level, allowing the backgate of PMOS transistors to be fed with a lower voltage, enabling stable operation and output of multiple high voltage levels.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Strength
If the PMOS transistor is designed to have a breakdown voltage for the VDDH level, then it can operate with high voltage, but it cannot be gate-controlled with the VDDL level
Solution Approach 1:
The circuit is divided into multiple PMOS transistors (first PMOS transistor and second PMOS transistor) with different breakdown voltage characteristics. The first PMOS transistor handles VDDL-level gate control while the second PMOS transistor handles VDDH-level output, segmenting the voltage handling functions to resolve the contradiction between high breakdown voltage requirement and low-voltage gate controllability
Solution Approach 2:
A switch circuit is introduced as an intermediary between the control signal source and the PMOS transistors. This switch circuit converts the VDDL-level control signal into appropriate control signals for both VDDL-level and VDDH-level PMOS transistors, enabling gate control of high-voltage transistors with low-voltage control signals
2Ease of operation
If the PMOS transistor is designed to be gate-controlled with the VDDL level, then it can be controlled easily, but it cannot operate with the VDDH level due to insufficient breakdown voltage
Solution Approach 1:
The circuit uses two separate PMOS transistors with different breakdown voltage ratings. The first PMOS transistor has breakdown voltage suitable for VDDL-level operation and gate control, while the second PMOS transistor has breakdown voltage suitable for VDDH-level operation, segmenting the voltage handling responsibilities
Solution Approach 2:
The switch circuit serves multiple functions: it acts as a level translator, a signal distributor, and a protective element. It enables the VDDL-level control signal to control both VDDL-level and VDDH-level PMOS transistors appropriately, providing universal control capability across different voltage domains
3Device complexity
If a single PMOS transistor is used to output both VDDL and VDDH levels, then the circuit is simple, but it cannot simultaneously fulfill breakdown voltage and gate control conditions
Solution Approach 1:
Instead of using a single PMOS transistor, the circuit segments the high-voltage output function into two separate PMOS transistors with different breakdown voltage characteristics. This segmentation allows each transistor to be optimized for its specific voltage level, ensuring reliable operation at both VDDL and VDDH levels while maintaining relatively simple circuit structure
Solution Approach 2:
The circuit changes the breakdown voltage parameter of PMOS transistors by selecting transistors with different breakdown voltage ratings for different output levels. The first PMOS transistor has breakdown voltage suitable for VDDL operation, while the second PMOS transistor has breakdown voltage suitable for VDDH operation, enabling stable output at multiple voltage levels
Data Source
AI summary
A buffer circuit includes a first node that receives a first voltage, a second node, an output node that receives the first voltage, a first transistor coupled between the first node and the second node, the first transistor having a backgate receiving the first voltage, and a second transistor coupled between the second node and the output node, the second transistor having a backgate receiving a second voltage being higher than the first voltage.