Buffer Circuit Power Control for Leakage Reduction
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Solution Overview
Problem
As data processing apparatus increase in complexity, the thinning of conductive lines in bus logic leads to increased resistance and capacitance, slowing signal propagation and causing power consumption issues due to leakage currents in buffer circuits, which existing techniques struggle to address effectively, especially when clock signals are not readily available for all buffer circuits.
Innovation Solution
A power control circuit is integrated within the bus logic that uses a pre-existing signal associated with data transfers to manage the power state of buffer circuits, allowing for fine-grained control and reducing leakage current by decoupling buffer circuits from power when the signal is invalid, thereby reducing power consumption without the need for additional clock buffering.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If buffer circuits are introduced to speed up signal propagation, then signal propagation speed is improved, but power consumption increases due to leakage currents
Solution Approach 1:
The buffer circuits are designed to dynamically change their operational state based on signal validity. When no valid signal is present, the buffer enters a low-power state by decoupling from the power supply, reducing leakage current. When a valid signal arrives, the buffer transitions to an active state to amplify and propagate the signal, thus adapting the power consumption to the actual need for signal transmission.
Solution Approach 2:
The invention changes the power supply parameter of the buffer circuits based on the validity of incoming signals. By using a power control circuit to monitor signal validity and adjust the power supply connection accordingly, the buffer's power consumption parameter is dynamically modified - disconnected when signals are invalid to reduce leakage, and connected when signals are valid to enable proper signal propagation.
2Loss of energy
If known leakage reduction techniques using clock signals are applied, then leakage current is reduced, but device complexity and layout requirements increase
Solution Approach 1:
The invention extracts the clock signal requirement from the leakage reduction mechanism. Instead of relying on clock signals to control buffer power states, the system uses the validity of incoming data signals themselves to control power consumption. This removes the need for separate clock distribution networks and associated buffering, significantly reducing device complexity and layout requirements while maintaining effective leakage current reduction.
Solution Approach 2:
The buffer circuits use the incoming data signals themselves to control their own power states. The validity of the input signal directly controls whether the buffer is powered or in low-power mode, eliminating the need for external control signals or clock networks. This self-service approach reduces system complexity while achieving leakage reduction.
Data Source
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AI summary
A data processing apparatus, bus logic and method are provided for controlling power consumption within a data processing apparatus. The data processing apparatus has a plurality of logic elements, at least one of the logic elements being an initiator logic element for initiating transfers, and at least one of the logic elements being a recipient logic element for receiving transfers. A communication path is provided between an initiator logic element and a recipient logic element to enable payload data the subject of a transfer to be passed from the initiator logic element to the recipient logic element. The communication path has at least one buffer circuit provided therein for propagating at least the payload data along the communication path. Further, a power control circuit is associated with the at least one buffer circuit, which is responsive to a control signal indicating whether the payload data on the communication path is valid. If the control signal indicates that the payload data is not valid, the power control circuit causes the associated at least one buffer circuit to enter a power saving state. The control signal is derived from at least one pre-existing signal associated with the transfer. This has been found to provide a particularly efficient and flexible technique for reducing leakage current in buffer circuits within the data processing apparatus.