Buffer Circuit With Transistor Capacitors For Voltage Drop Reduction
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Solution Overview
Problem
Conventional semiconductor devices face challenges in enhancing current driving capability while minimizing chip size, as parallel transistors with shared source regions lead to increased voltage drops and chip size expansion due to the need for shallow trench isolation to prevent these drops.
Innovation Solution
The proposed solution involves an inverter buffer circuit design where transistors of different polarities are coupled in parallel, with specific transistors acting as capacitors between power supply voltage lines to compensate for voltage fluctuations, and additional transistors with shared source and drain regions functioning as power voltage compensation capacitors to manage voltage transitions without increasing chip size.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Power
If transistors are coupled in parallel to enhance current driving capability, then current driving capability is improved, but voltage drop increases due to increased current density at shared source regions
Solution Approach 1:
The patent segments the source regions of adjacent transistors by introducing shallow trench isolation (STI) structures between them. This division separates the previously shared source region into distinct isolated regions, reducing current density concentration and minimizing voltage drop while maintaining the parallel transistor configuration for enhanced current driving capability
Solution Approach 2:
The shallow trench isolation structure acts as an intermediary element inserted between adjacent transistor source regions. This STI structure mediates the electrical interaction between neighboring transistors, providing electrical isolation that prevents excessive current density accumulation and voltage drop at the source regions
2Loss of energy
If source regions are separated to avoid large voltage drop, then voltage drop is reduced, but chip size increases due to additional isolation structures
Solution Approach 1:
The patent applies shallow trench isolation selectively and locally only at specific positions between adjacent transistor source regions, rather than uniformly across the entire chip. This localized application achieves the necessary voltage drop reduction while minimizing the additional area occupied by isolation structures, thus controlling chip size expansion
3Power
If multiple transistors are coupled in parallel, then current driving capability is enhanced, but layout complexity increases due to separation requirements
Solution Approach 1:
The patent merges the isolation function into the existing transistor fabrication process by integrating shallow trench isolation formation with the standard CMOS manufacturing steps. This combination allows the isolation structures to be formed simultaneously with other device components, reducing layout complexity while maintaining the parallel transistor configuration for enhanced current driving capability
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This design effectively suppresses voltage fluctuations and maintains efficient power usage without increasing chip size, addressing the issue of voltage drops and layout complexity in conventional semiconductor devices.
Implementation Method 1
Gates of the p-channel and n-channel field-effect transistors are coupled in common to an input node. Gates of p-channel field-effect transistors are coupled in common to another power supply voltage line for power supply voltage... Gates of n-channel field-effect transistors are coupled in common to another power supply voltage line for reference voltage... Additionally, a buffer circuit according to an embodiment includes... transistors with shared source and drain regions functioning as power voltage compensation capacitors
Data Source
AI summary
Apparatuses for providing buffer circuits a semiconductor device are described. An example apparatus includes a plurality of inverters and a transistor having one diffusion region coupled to a diffusion region of a transistor of one inverter of the plurality of inverters, another diffusion region coupled to a diffusion region of a transistor of another inverter of the plurality of inverters. The transistor having a gate coupled to one power supply voltage and diffusion regions coupled to another power supply voltage functions as a power voltage compensation capacitor.