Buffer Circuit Voltage Configuration for Image Sensor Gate Insulation
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Solution Overview
Problem
Existing image sensing apparatuses face damage to gate insulating films of transistors when widening the dynamic range of pixels, due to excessive electric fields applied during the operation of transfer MOS transistors, leading to reduced driving capability and increased manufacturing costs.
Innovation Solution
The image sensing apparatus employs a buffer circuit with specific voltage configurations for PMOS and NMOS transistors, ensuring that the electric field strengths across their gate insulating films do not exceed their withstand voltages, thereby preventing damage and maintaining driving capability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a negative voltage is supplied to the gate of the transfer MOS transistor to turn it off and widen the dynamic range, then the dynamic range of each pixel is improved, but the gate insulating film of the buffer circuit transistors is damaged due to excessive electric field
Solution Approach 1:
The patent changes the voltage parameters of the buffer circuit transistors. Specifically, it supplies a negative voltage to the source of the NMOS transistor and a positive voltage to the source of the PMOS transistor, thereby controlling the gate-source voltage differences to remain within safe limits and prevent gate insulating film damage while achieving the desired transfer transistor turn-off function
Solution Approach 2:
The patent introduces voltage supply circuits as intermediary components that mediate between the control signal and the buffer circuit transistors. These intermediaries adjust the voltage levels appropriately to ensure that the electric field across the gate insulating films remains within withstand limits while still enabling the transfer transistor to be turned off for dynamic range expansion
Data Source
AI summary
An image sensing apparatus comprises a pixel and a driving unit, wherein the driving unit includes a buffer circuit including a first PMOS transistor and a first NMOS transistor, and letting V3 be a voltage supplied to a gate of the first NMOS transistor to supply a transfer signal for turning off the transfer MOS transistor to the transfer control line, V4 be a voltage supplied to a gate of the first PMOS transistor to supply a transfer signal for turning on the transfer MOS transistor to the transfer control line, Vthp1 be a threshold voltage of the first PMOS transistor, and Vthn1 be a threshold voltage of the first NMOS transistor, (V2+Vthn1)<V3<V1 and V2<V4<(V1+Vthp1) are satisfied.