Buffer Control Circuit for Refresh Current Reduction

Solution Overview

Problem

Semiconductor devices face high current consumption during refresh operations due to the need for active buffer enablement across all banks, which is inefficient and consumes unnecessary power.

Innovation Solution

An electronic device with a command generation circuit and buffer control circuit that generates specific enable signals for buffer groups during all-bank refresh operations, allowing for selective enablement and disablement of buffers based on logic level combinations of internal chip selection signals and command addresses, thereby reducing current consumption.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If buffers are enabled during refresh operations to receive command addresses, then the device can perform refresh operations, but current consumption increases

Engineering Contradiction:

Improverefresh operation capabilityVSAvoidcurrent consumption

Core Design Contradiction:

ReliabilityVSUse of energy by moving object

Solution Approach 1:

The patent applies dynamics by making the buffer enable state changeable based on operation type. During refresh operations, the buffer enable signal is dynamically adjusted to disable buffers for specific command addresses (CA[1:0]=00b) while keeping them enabled for other addresses, allowing the system to adapt its buffer usage to the current operational context and reduce unnecessary power consumption.

Inventive Principle:

Principle #15Dynamics

Solution Approach 2:

The patent applies local quality by selectively disabling only specific buffers that handle particular command addresses during refresh operations, rather than disabling all buffers globally. The buffer control circuit generates differentiated enable signals based on the command address being processed, ensuring that only the locally relevant buffers (those handling refresh command addresses) are disabled while others remain operational.

Inventive Principle:

Principle #3Local quality

2Adaptability or versatility

If all buffers are enabled during refresh operations, then all command addresses can be processed, but power consumption increases unnecessarily

Engineering Contradiction:

Improvecommand address processing capabilityVSAvoidpower consumption

Core Design Contradiction:

Adaptability or versatilityVSLoss of energy

Solution Approach 1:

The patent applies partial action by enabling buffers only for the specific command addresses that need processing during refresh operations. Instead of enabling all buffers unnecessarily, the system uses the buffer control circuit to generate enable signals selectively based on the command address being processed, applying buffer enablement only where needed and reducing overall power consumption.

Inventive Principle:

Principle #16Partial or excessive action

3Use of energy by moving object

If buffers are disabled during refresh operations, then current consumption is reduced, but the device cannot perform refresh operations

Engineering Contradiction:

Improvecurrent consumptionVSAvoidrefresh operation capability

Core Design Contradiction:

Use of energy by moving objectVSReliability

Solution Approach 1:

The patent applies dynamics by making the buffer enable state changeable based on operation type. During refresh operations, the buffer enable signal is dynamically adjusted to disable buffers for specific command addresses (CA[1:0]=00b) while keeping them enabled for other addresses, allowing the system to adapt its buffer usage to the current operational context and reduce unnecessary power consumption.

Inventive Principle:

Principle #15Dynamics

Data Source

PatentUS11705182B2Electronic device for controlling command input

Publication Date: 2023.07.18 SK HYNIX INC

AI summary

An electronic device includes a command generation circuit configured to generate a refresh command and a driving control signal, which are enabled during an all-bank refresh operation, according to a logic level combination of an internal chip selection signal and an internal command address. The electronic device also includes a buffer control circuit configured to generate, from the refresh command and the driving control signal, a first buffer enable signal for enabling a first group of buffers and a second buffer enable signal for enabling a second group of buffers.