Buffer Circuit Delay Control for Frequency Divider Phase Noise
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Wireless fidelity (Wi-Fi) transmitters face challenges in reducing phase noise introduced by frequency dividing circuits, which degrades the quality of output signals due to noise amplification during the frequency division process.
Innovation Solution
A buffer circuit is introduced, comprising a buffer and control circuits that perform reverse gain amplification and delay control on the frequency-divided signals, using square wave signals with a 50% duty ratio to cancel noise generated by the frequency divider, thereby improving the phase noise performance of the output signal.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If frequency division is performed on clock signal, then IQ signals are obtained for wireless transmission, but phase noise is introduced and amplified by the PPA circuit
Solution Approach 1:
The patent captures the phase noise signal generated by the frequency dividing circuit and uses it as a feedback input to the buffer circuit. By processing this noise signal through the buffer with controlled delay, the system converts the harmful phase noise into a useful cancellation signal that can be subtracted from the main signal path, thereby eliminating the adverse effect while maintaining the frequency division function
Solution Approach 2:
The patent implements a feedback mechanism where the output of the frequency dividing circuit is fed back to the buffer circuit. The buffer circuit processes this feedback signal with specific delay characteristics, and the processed feedback is then combined with the main signal path to cancel out the phase noise. This closed-loop feedback system continuously monitors and compensates for phase noise, resolving the contradiction between maintaining frequency division and eliminating noise
2Power
If PPA circuit amplifies the frequency-divided clock signal, then signal strength is increased, but the noise is further amplified
Solution Approach 1:
The patent introduces a buffer circuit as an intermediary element between the frequency dividing circuit and the PPA amplifier. This buffer circuit processes the signal to extract and isolate the phase noise component before it enters the amplification stage. By acting as an intermediary, the buffer prevents the noise from being amplified along with the signal, allowing the PPA to amplify only the clean signal component
Solution Approach 2:
The patent segments the signal processing into distinct functional paths: one path handles the main signal amplification through the PPA circuit, while another path processes the noise component through the buffer circuit. This segmentation allows independent optimization of each path - the main path achieves high gain while the noise path generates cancellation signals, thereby resolving the contradiction between amplification and noise control
3Object-generated harmful factors
If buffer circuit performs reverse gain amplification and delay control, then phase noise is canceled, but circuit complexity increases
Solution Approach 1:
The buffer circuit in the patent is designed to perform multiple functions simultaneously: it provides reverse gain amplification to generate the cancellation signal, introduces controlled delay to align the noise cancellation timing, and processes the feedback signal from the frequency divider. By consolidating these multiple functions into a single buffer circuit module, the patent achieves effective phase noise cancellation without proportionally increasing circuit complexity
Solution Approach 2:
The patent merges the noise cancellation function with the existing signal buffering function. Instead of adding a separate noise cancellation circuit, the design integrates the cancellation capability into the buffer circuit that already exists in the signal path. This merging approach achieves phase noise cancellation while minimizing the increase in overall circuit complexity, as the buffer circuit serves dual purposes
Data Source
AI summary
A buffer circuit, a frequency dividing circuit, and a communications device are disclosed. The buffer circuit includes a buffer, a first control circuit, and a second control circuit. The buffer is coupled to a frequency divider, and the buffer is configured to receive a first signal output by the frequency divider, and output a fourth signal by using an output terminal of the buffer circuit when driven by the first signal, where the first signal is obtained by the frequency divider by performing frequency division on a group of differential signals, and the differential signals include a second signal and a third signal. The first control circuit is configured to perform delay control on a rising edge of the fourth signal based on the second signal. The second control circuit is configured to perform delay control on a falling edge of the fourth signal based on the third signal.