Buffer Dependency Model for Accurate SoC Traffic Simulation
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Solution Overview
Problem
Existing test systems for systems-on-chip fail to accurately model dependencies between transactions in initiators like CPUs and GPUs, leading to performance variations that are not representative when the system changes, as they do not account for resource availability and buffer-related dependencies.
Innovation Solution
Introduce dependencies by modifying data traffic timings based on resource availability and buffer occupancy, specifically using counters to represent buffer sizes and updating timings when buffers are full, to simulate resource access stalls, thereby improving the accuracy of system modeling.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If data traffic is generated from real system traces or example models, then the model can be kept simple and easy to use, but dependencies between transactions within initiators are not captured, leading to inaccurate performance representation when the system changes
Solution Approach 1:
A buffer dependency model is introduced as an intermediary component between the data traffic generator and the system model. This model monitors buffer occupancy and introduces artificial dependencies by stalling data traffic when buffers are full, thereby capturing buffer-related dependencies without requiring complex instrumentation of the actual initiators. The intermediary adds realistic timing variations while keeping the overall model structure simple.
2Measurement precision
If adaptive trace is used to capture realistic dependencies between transactions, then measurement precision improves, but device complexity increases significantly as the actual system must be implemented and instrumented
Solution Approach 1:
Instead of implementing and instrumenting the actual initiators to capture dependencies, the patent creates a simplified copy or model of the buffer dependency behavior. The buffer dependency model replicates the essential characteristic of buffer-related stalls without needing to copy the entire initiator architecture. This approach captures the critical dependency information while avoiding the complexity of full system instrumentation.
3Measurement precision
If buffer dependencies are modeled by stalling data traffic when buffers are full, then the accuracy of performance prediction improves, but the processing time increases due to introduced delays
Solution Approach 1:
The buffer dependency model performs preliminary analysis of buffer occupancy states before data traffic is processed. By pre-determining when buffers will be full and proactively introducing stalls at these points, the model avoids the need for complex real-time simulation of buffer operations. This preliminary action approach captures the essential timing behavior while reducing the overall computational burden of the model.
Data Source
AI summary
Timings of data traffic in a test system are modified by introducing dependencies that would arise in response to data requiring access to a resource comprising a buffer for storing pending data related to an access to the resource that cannot currently complete. A maximum value of a counter is set to a value corresponding to the buffer size. Data traffic is input, and the counter is updated in response to the data requiring the resource and being stored in the buffer and in response to the data traffic indicating a buffer entry has become available. Where the data requires the buffer and the counter is at its maximum value indicating the buffer is full, a timing of the data access requiring the buffer is modified indicating that the data is stalled until the buffer has capacity again, and the data traffic is updated with the modified timing.