Buffer-Die Semiconductor Package for High Chip Stack Stability

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Solution Overview

Problem

The challenge in semiconductor packaging is to increase the number of stacked semiconductor chips while minimizing defects such as warpage, dishing, and erosion, which occur due to the thickness increase and adhesion issues between chips.

Innovation Solution

A semiconductor package structure is proposed, comprising a buffer die with sequentially stacked core die blocks, each including multiple semiconductor chips and gap filling portions to prevent adhesion defects, and a molding member covering the outer surfaces, which enhances structural stability and reduces chip alignment and thickness-related issues.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If the number of stacked semiconductor chips is increased, then the performance of the semiconductor package is improved, but the thickness of the semiconductor chip needs to be decreased which causes defects such as warpage, dishing, and erosion

Engineering Contradiction:
Improvenumber of stacked semiconductor chipsVSAvoidchip thickness control
Core Design Contradiction:
ProductivityVSManufacturing precision

Solution Approach 1:

A buffer die is introduced as an intermediary component between the substrate and the stacked core die blocks. This buffer die absorbs the thickness variations and provides a stable bonding surface, enabling stacking of multiple chips without requiring each individual chip to be extremely thin, thus preventing warpage and dishing defects

Inventive Principle:
Principle #24Intermediary (Mediator)

Solution Approach 2:

The semiconductor package is segmented into distinct functional blocks: a buffer die and multiple core die blocks stacked on top of it. This segmentation allows the buffer die to handle the mechanical stress and thickness management, while the core die blocks can be optimized for their specific functions, enabling higher stacking counts without compromising chip integrity

Inventive Principle:
Principle #1Segmentation

2Productivity

If the number of stacked semiconductor chips is increased, then the performance of the semiconductor package is improved, but defects such as warpage, dishing, and erosion occur

Engineering Contradiction:
Improvenumber of stacked semiconductor chipsVSAvoiddefect rate
Core Design Contradiction:
ProductivityVSReliability

Solution Approach 1:

The buffer die serves as a mediator that isolates the stacked core die blocks from the substrate, providing mechanical support and distributing stress evenly. This reduces warpage and dishing in the stacked chips, thereby improving reliability while maintaining high stacking counts

Inventive Principle:
Principle #24Intermediary (Mediator)

Solution Approach 2:

The invention changes the structural parameters of the package by introducing a buffer die with specific thickness and material properties that differ from both the substrate and the core die blocks. This parameter change allows for better stress management and defect prevention in multi-chip stacks

Inventive Principle:
Principle #35Parameter changes

3Reliability

If gap filling portions are added to cover outer side surfaces, then adhesion defects are prevented, but the device complexity increases

Engineering Contradiction:
Improveadhesion qualityVSAvoidpackage structure
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

Gap filling portions are introduced as intermediary materials that fill the spaces between adjacent core die blocks. These gap fillers provide mechanical support and improve adhesion between chips without requiring complex bonding processes, thus enhancing reliability while keeping the manufacturing process relatively simple

Inventive Principle:
Principle #24Intermediary (Mediator)

Data Source

PatentUS20240413026A1Semiconductor package and method of manufacturing the semiconductor package
Publication Date: 2024.12.12 SAMSUNG ELECTRONICS CO LTD
  • US20240413026A1 patent drawing
  • US20240413026A1 patent drawing
  • US20240413026A1 patent drawing

AI summary

A semiconductor package includes a buffer die, a plurality of core die blocks sequentially stacked on the buffer die, and a molding member on the buffer die and covering outer surfaces of the plurality of core die blocks. Each of the plurality of core die blocks includes a first semiconductor chip, a second semiconductor chip disposed on the first semiconductor chip and a first gap filling portion, a third semiconductor chip disposed on the second semiconductor chip and a second gap filling portion, and a fourth semiconductor chip disposed on the third semiconductor chip.