Buffer Circuit Feedback for Duty Cycle Distortion Correction

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Solution Overview

Problem

Conventional buffer circuits in semiconductor devices do not correct duty cycle distortions in input signals, leading to decreased margin and potential malfunctions in semiconductor devices.

Innovation Solution

A buffer circuit comprising an amplifier circuit, a charge pump circuit, and a driver circuit that amplifies the difference between an input signal and a reference signal, generates a control signal based on the duty cycle, and adjusts the pull-up and pull-down strengths to correct the duty cycle of the output signal.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Power

If conventional buffer circuits are used to amplify signals, then signal amplification is achieved, but duty cycle distortion occurs in the output signal

Engineering Contradiction:
Improvesignal amplificationVSAvoidduty cycle accuracy
Core Design Contradiction:
PowerVSManufacturing precision

Solution Approach 1:

The patent implements a feedback mechanism where the output signal is fed back to a duty cycle detection circuit that generates a control signal. This control signal adjusts the operation of the amplifier circuit to correct duty cycle distortion, creating a closed-loop system that maintains accurate duty cycle while providing signal amplification

Inventive Principle:
Principle #23Feedback

Solution Approach 2:

The patent changes the operating parameters of the amplifier circuit dynamically by adjusting bias currents and voltages based on the detected duty cycle error. The control signal modifies these parameters in real-time to compensate for duty cycle distortion and maintain the desired duty cycle in the output signal

Inventive Principle:
Principle #35Parameter changes

2Device complexity

If duty cycle offset is not corrected, then circuit complexity is reduced, but set margin and hold margin decrease

Engineering Contradiction:
Improvecircuit complexityVSAvoidmargin stability
Core Design Contradiction:
Device complexityVSReliability

Solution Approach 1:

The patent introduces an intermediary duty cycle detection and control circuit that sits between the amplifier and the load. This intermediary component specifically addresses the duty cycle correction function without requiring complete redesign of the entire system, adding only the necessary elements for margin stability

Inventive Principle:
Principle #24Intermediary (Mediator)

3Ease of operation

If duty cycle offset accumulates during signal processing, then device operation is simpler, but malfunction occurs

Engineering Contradiction:
Improvedevice operationVSAvoidmalfunction prevention
Core Design Contradiction:
Ease of operationVSReliability

Solution Approach 1:

The patent applies preliminary correction action by detecting duty cycle distortion early in the signal path and correcting it before the signal undergoes further processing. The duty cycle correction is performed proactively to prevent accumulation of errors that would lead to malfunction in subsequent device operations

Inventive Principle:
Principle #10Preliminary action

Data Source

PatentUS8358162B2Buffer circuit and duty cycle correction method using same
Publication Date: 2013.01.22 SAMSUNG ELECTRONICS CO LTD
  • US8358162B2 patent drawing
  • US8358162B2 patent drawing
  • US8358162B2 patent drawing

AI summary

A buffer circuit includes an amplifier circuit amplifying a difference between an input signal and a reference signal, providing a branch current that varies with a duty cycle of the input signal, and outputting a preliminary output signal on the basis of the amplified difference. The buffer circuit also includes a charge pump circuit charging/discharging a control node in response to the branch current to provide a control signal. The buffer circuit also includes a driver circuit configured to control pull-up strength and pull-down strength for the preliminary output signal based on control signal to thereby correct the duty cycle of the preliminary output signal in relation to a target duty cycle.