Buffer Circuit With Duty-Balanced Output Drive Control
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Solution Overview
Problem
Conventional buffer circuits experience duty imbalance in output signals due to offsets in the reference voltage, leading to signal integrity deterioration and potential data recognition errors.
Innovation Solution
A buffer circuit design that includes an amplification unit and a driver with adjustable pull-up and pull-down driving strengths, controlled by a third transistor in response to changes in the reference voltage, ensuring balanced high and low pulse widths of the output signal.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the reference voltage VREF is increased by a positive offset, then the amplification unit outputs a signal with unbalanced duty cycle, but the driver inverts the signal to produce an output with balanced duty cycle
Solution Approach 1:
The patent converts the harmful effect of reference voltage offset into a beneficial control signal. The offset in VREF, which originally caused duty cycle imbalance, is now used to control the driving strength of the pull-up and pull-down transistors. When a positive offset occurs, the control unit increases pull-down strength and decreases pull-up strength to compensate, transforming the harmful offset into a useful compensation mechanism that maintains balanced output duty cycle without requiring additional offset detection circuits.
Solution Approach 2:
The patent implements a feedback mechanism where the reference voltage VREF, which contains the offset information, is fed back to the control unit. The control unit continuously monitors VREF and dynamically adjusts the driving strength of the output transistors based on the offset condition. This closed-loop feedback ensures that the output signal maintains a balanced duty cycle despite variations in the reference voltage, improving signal integrity without complex external correction circuits.
2Reliability
If the driver inverts the amplified signal to correct duty imbalance, then the output duty cycle is balanced, but the signal propagation delay increases
Solution Approach 1:
The patent applies preliminary action by pre-adjusting the driving strength of the pull-up and pull-down transistors based on the reference voltage offset condition before the signal transition occurs. The control unit calculates the required driving strength adjustment in advance and configures the transistor parameters accordingly, so that when the signal needs to be driven, the transistors are already optimally configured. This eliminates the need for additional inversion stages and reduces signal propagation delay while maintaining accurate duty cycle.
3Reliability
If the driving strength of pull-up or pull-down is increased to compensate for offset, then the output duty cycle is balanced, but the power consumption increases
Solution Approach 1:
The patent implements dynamic control of the driving strength by using voltage-controlled resistors or transistors whose resistance or conductance can be dynamically adjusted based on the reference voltage offset. Instead of using fixed high-strength drivers that consume excessive power, the system continuously adapts the driving strength to the minimum required level to maintain duty cycle balance. This dynamic adjustment reduces power consumption while ensuring reliable duty cycle correction under varying offset conditions.
Data Source
AI summary
A buffer circuit includes an amplification unit configured to amplify and output a difference between an input signal and a reference voltage; and a driver configured to drive an output node in response to the output of the amplification unit and be controlled in at least one of a pull-up driving strength and a pull-down driving strength at the output node in response to the reference voltage.