Semiconductor Output Buffer Fault Detection Without Comparators
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Solution Overview
Problem
Existing semiconductor devices equipped with protection circuits for short circuits and ground faults face issues with erroneous detection and restricted usage due to circuit size and cost increases, particularly when dealing with varying speaker wiring resistances and load resistances.
Innovation Solution
A semiconductor device incorporating a short circuit detection circuit that utilizes a PMOS transistor and NMOS transistors to evaluate potential differences between output terminals, eliminating the need for comparators and reference voltages, thereby maintaining a low-cost and compact design while accurately detecting short circuits and ground faults.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If a comparator is used to evaluate short circuits between terminals, then detection accuracy is improved, but circuit size and cost increase
Solution Approach 1:
The patent extracts the essential detection function from a complex comparator circuit and implements it using a simplified evaluation circuit that only requires basic logic gates. This extraction approach maintains the core short circuit detection capability while removing unnecessary circuit complexity, thereby reducing circuit size and cost while preserving detection accuracy.
Solution Approach 2:
The patent replaces expensive comparator components with cheaper, simpler logic gate-based evaluation circuits. This substitution uses readily available, low-cost digital logic elements that can perform the same detection function without requiring precision analog components, thus reducing overall circuit cost and complexity while maintaining adequate detection performance.
2Reliability
If a protection circuit with comparator is implemented, then reliability is improved, but manufacturing cost increases
Solution Approach 1:
The patent substitutes expensive comparator-based protection circuits with inexpensive logic gate-based evaluation circuits. This replacement uses standard digital logic components that are cheaper to manufacture and integrate, thereby reducing production costs while maintaining the essential protection function against short circuits and ground faults.
Solution Approach 2:
The patent changes the detection parameter approach from analog voltage comparison (requiring precision comparators) to digital logic-level evaluation. This parameter transformation allows the use of simpler, cheaper digital logic components instead of precision analog components, reducing manufacturing costs while preserving the protection function through different detection methodology.
3Reliability
If existing protection circuits are used, then ground fault detection is improved, but adaptability to various load resistances deteriorates
Solution Approach 1:
The patent designs an evaluation circuit that universally handles multiple detection functions (short circuit between terminals, ground fault at terminal 1, ground fault at terminal 2) using a single unified logic structure. This universal design allows the circuit to adapt to various speaker wiring resistances and load conditions without requiring separate detection circuits for each fault type, thereby improving adaptability while maintaining comprehensive protection capability.
Data Source
AI summary
A semiconductor device includes: a first buffer at which a predetermined signal is input and that outputs a first output signal; a second buffer at which an inverted signal of the predetermined signal is input and that outputs a second output signal; and a short circuit detection circuit that, in accordance with a potential difference between the first output signal and the second output signal, outputs a short circuit evaluation signal evaluating whether or not there is a ground fault in at least one of a first terminal at an output side of the first buffer or a second terminal at an output side of the second buffer or evaluating whether or not there is a short circuit between the first terminal and the second terminal.