Buffer Fullness Signaling in Video Decoding

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Solution Overview

Problem

Existing video codecs and coding standards are inflexible and unable to adapt to variable peak bit rates and buffer sizes in modern video applications, leading to resource wastage and unsuitable delay times, particularly in streaming over networks with fluctuating bandwidth and diverse device capabilities.

Innovation Solution

The signaling of buffer fullness is done relative to the decoder buffer size, using a leaky bucket model that includes transmission rate, buffer capacity, and buffer fullness elements, allowing for more efficient adaptation to varying conditions.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If a fixed constant bit rate is used for video transmission, then decoding stability is ensured, but adaptability to varying network bandwidth and device buffer sizes deteriorates

Engineering Contradiction:
Improvedecoding stabilityVSAvoidadaptability to network conditions
Core Design Contradiction:
ReliabilityVSAdaptability or versatility

Solution Approach 1:

The patent implements dynamic buffer fullness signaling that adjusts transmission parameters based on real-time network conditions and device capabilities. The system transitions from fixed constant bit rate to variable bit rate controlled by buffer fullness metrics, allowing the encoder to adapt transmission rate dynamically while maintaining decoding stability through buffer management.

Inventive Principle:
Principle #15Dynamics

Solution Approach 2:

The patent changes the parameter representation from absolute buffer fullness values to fractional buffer fullness (ratio of current buffer occupancy to buffer capacity). This parameter transformation enables scalable adaptation across different network conditions and device types, resolving the contradiction between stability and adaptability.

Inventive Principle:
Principle #35Parameter changes

2Measurement precision

If absolute buffer fullness values are signaled, then precise buffer control is achieved, but signaling efficiency and adaptability to different buffer sizes deteriorates

Engineering Contradiction:
Improvebuffer control precisionVSAvoidsignaling efficiency
Core Design Contradiction:
Measurement precisionVSAdaptability or versatility

Solution Approach 1:

The patent transforms the buffer fullness parameter from absolute values (number of bits) to fractional values (ratio between 0 and 1 representing buffer occupancy proportion). This parameter change maintains precise buffer control while improving signaling efficiency, as the fractional representation is scale-invariant and adapts automatically to different buffer sizes without requiring reconfiguration.

Inventive Principle:
Principle #35Parameter changes

3Reliability

If large buffer sizes are used to handle peak bit rates, then transmission reliability is improved, but device resource consumption and delay increase

Engineering Contradiction:
Improvetransmission reliabilityVSAvoidbuffer delay
Core Design Contradiction:
ReliabilityVSLoss of time

Solution Approach 1:

The patent implements feedback control through buffer fullness signaling, where the encoder monitors buffer occupancy and adjusts transmission rate accordingly. This feedback mechanism allows the system to maintain transmission reliability by preventing buffer underflow while minimizing buffer size and delay, as the buffer only holds what is necessary based on actual transmission needs rather than pre-allocating large fixed buffers.

Inventive Principle:
Principle #23Feedback

Data Source

PatentUS8345754B2Signaling buffer fullness
Publication Date: 2013.01.01 MICROSOFT TECHNOLOGY LICENSING LLC
  • US8345754B2 patent drawing
  • US8345754B2 patent drawing
  • US8345754B2 patent drawing

AI summary

Techniques and tools are described for signaling hypothetical reference decoder parameters for video bitstreams, including signaling of buffer fullness. For example, a buffer size syntax element indicates a decoder buffer size, and a buffer fullness syntax element indicates a buffer fullness as a fraction of the decoder buffer size. As another example, buffer fullness is signaled in one or more entry point headers and other hypothetical reference decoder parameters are signaled in a sequence header.