Output Buffer Impedance Calibration With Dual Reference Potential Circuit

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Solution Overview

Problem

Existing calibration circuits for output buffer circuits in semiconductor devices face challenges in achieving precise impedance adjustment due to manufacturing conditions, temperature fluctuations, and power source variations, leading to inappropriate impedance settings during calibration operations, especially when the reference-potential generating circuit is activated intermittently.

Innovation Solution

The semiconductor device incorporates a calibration circuit with a reference-potential generating circuit having two potential generating units, one activated by an enable signal and the other always active, ensuring immediate reference potential availability for comparison circuits, allowing for precise impedance control of replica buffer circuits and subsequently the output buffer circuit, while minimizing power consumption.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Use of energy by moving object

If the reference-potential generating circuit is activated intermittently in response to calibration commands, then power consumption is reduced, but the reference potential may not be ready immediately causing inappropriate impedance settings

Engineering Contradiction:

Improvepower consumptionVSAvoidimpedance setting accuracy

Core Design Contradiction:

Use of energy by moving objectVSReliability

Solution Approach 1:

The reference-potential generating circuit is activated in advance before the calibration command is actually needed, so that the reference potential is already stable and ready when calibration is initiated. This preliminary activation ensures that when calibration occurs, the reference potential is immediately available, preventing inappropriate impedance settings while allowing the circuit to remain active long enough to establish stable potential.

Inventive Principle:

Principle #10Preliminary action

Solution Approach 2:

The activation timing of the reference-potential generating circuit is made dynamic rather than static. Instead of being continuously active or only activated exactly at calibration moment, the circuit is activated at an optimal time before calibration based on predicted calibration commands, adapting its activation schedule to balance power consumption with readiness requirements.

Inventive Principle:

Principle #15Dynamics

2Speed

If the reference-potential generating circuit is continuously activated, then reference potential is always ready for immediate comparison, but power consumption increases

Engineering Contradiction:

Improvereference potential generation speedVSAvoidpower consumption

Core Design Contradiction:

SpeedVSUse of energy by moving object

Solution Approach 1:

Inventive Principle:

Principle #10Preliminary action

Solution Approach 2:

Instead of continuous activation, the reference-potential generating circuit is activated periodically or event-driven based on predicted calibration commands. The circuit activates before calibration is needed, maintains the reference potential during calibration, and then can be deactivated or entered into a low-power state, converting continuous operation into periodic operation to reduce overall power consumption.

Inventive Principle:

Principle #19Periodic action

Data Source

PatentUS8390318B2Semiconductor device having calibration circuit for adjusting output impedance of output buffer circuit

Publication Date: 2013.03.05 LONGITUDE LICENSING LTD

AI summary

Disclosed herein is a device that includes a replica buffer circuit that drives a calibration terminal, a reference-potential generating circuit that generates a reference potential, a comparison circuit that compares a potential appearing at the calibration terminal with the reference potential, and a control circuit that changes an output impedance of the replica buffer circuit based on a result of a comparison by the comparison circuit. The reference-potential generating circuit includes a first potential generating unit activated in response to an enable signal and a second potential generating unit activated regardless of the enable signal, and an output node of the first potential generating unit and an output node of the second potential generating unit are commonly connected to the comparison circuit.